Formal and Joint Verification of Control Programs and Supervision Interfaces for Socio-technical Systems Components

Mesli-Kesraoui, Soraya; Toguyéni, Armand; Bignon, Alain; Oquendo, Flávio; Kesraoui, Djamal; Berruet, Pascal

doi:10.1016/j.ifacol.2016.10.603

Cited by 8 publications

(9 citation statements)

References 6 publications

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“…Existing works focus on control logic programming stage [37], [39], [56], [75], [112], [114], [117], [133], [143], [145], aiming to detect malicious code, and conform to safety and functionality requirements. The interests of formal verification span from different programming languages, specifications, and verification frameworks, evolving with the technology, standards, and requirements.…”

Section: B Research Efforts 1) Stagementioning

confidence: 99%

“…Later works assume IEC-61499 defined languages with DCS [43], [48], [133], model-driven development [75], timers [75], [134], [143], multitask control logic [115], and incorporating machine learning [103]. More recent works assume interactions and communications [47], [67], multilayer verification [114], complete verification frameworks [56], [112], [145].…”

Section: B Research Efforts 1) Stagementioning

confidence: 99%

“…i) 2016-2017: In 2016, Mesli [114] first realized the need of multi-layer formal verification of control logic. Mesli proposed joint verification of supervision interfaces (e.g., HMI) and the controller ladder programs.…”

Section: B Research Efforts 1) Stagementioning

confidence: 99%

“…Surveying the related papers published in the last thirty years, we found that applying formal verification to control logic has made great progress [142], including automatic formalization of complete control logic languages defined in IEC-61131 [39], and hybrid models that support transition from a continuous part to a discrete part of a system [92]. It is also encouraging to see prototypes of joint formal verification for both PLC and SCADA [114], and user-friendly verification with simulation and visualization. Nevertheless, we discovered multiple security challenges for formal verification based defenses, including synchronization, multitask, and etc.…”

Section: Introductionmentioning

confidence: 97%

“…AICE Model checking solution CTL Model Checker Chemical Brinksma'00 [45] SPIN Non-real-time model checking SPIN, Promela Chemical Bauer'04 [36] ISSTAE Model checking for timed and untimed SFC Cadence SMV, Uppaal Chemical Rawlings'18 [126] JCCE Handle combined invariance and reachability symbolic model checking, Chemical Rausch'98 [125] ACC Model checking solution SMV, Petri Net Manufacturing Bonfe'03 [43] ICEFTA Compare IEC 61131 and IEC 61499 SMV Manufacturing Cengic'06 [48] ICETFA Runtime environment for IEC 61499 Supremica (automata) Manufacturing Carlsson'12 [47] TII [112] NDSS Trusted safety verification platform TEG, symbolic execution Other Mechatronic Mesli'16 [114] HMS Multiple layer verification Uppaal Other mechatronics Darvas'17 [61] PPEECS ST to represent all languages PLCverif Other mechatronics Kottler'17 [98] SoutheastCon Detect malfunctions by intruding NuSMV NuSMV Other mechatronics Vyatkin'99 [133] ICETFA Verification for IEC 61499 Petri Net, CTL Generic Rossi'00 [127] ICAM Model checking using LD Cadence SMV Generic Bender'08 [37] MDAFA Model checking to detect race condition Petri net (TPN), Tina tool Generic Biha'11 [40] ACSAC Formal semantics for IL in Coq Coq with on-delay timers Generic Wang'13 [135] ACSAC Formal semantics in BIP models BIP Generic Kuzmin'13 [99] ACCS* Construct and verify PLC programs Cadence SMV Generic Darvas'16 [59] PMS Generic model representation PLCverif Generic Bohlender'18 [42] DES Mode abstraction for impact computation SMT Generic Galvao'18 [70] HELIX Review of plant models in form verification N/A Generic Luckeneder'18 [104] SAC Adaptive Cruise Control with model checking N/A Generic Huang'19 [87] Access Formal semantics of ST applied in C, Java N/A Generic Garcia'19 [72] ICCPS Translate DC code to PLC code and vice versa Theorem prover KeYmaera X Generic Zhang'19 [143] S&P Automated safety vetting of PLC code BUILDTSEQS on TPTL Generic Lamperiere'99 [100] ECC Survey SFC and LD validation N/A Survey Frey'00 [69] ICSMC survey based on A-F-M N/A Survey Mader'00 [106] DES Classification criteria of modelling N/A Survey ...…”

mentioning

confidence: 99%

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SoK: Attacks on Industrial Control Logic and Formal Verification-Based Defenses

Sun¹,

Mera²,

Lu³

et al. 2020

Preprint

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Control logic programs play a critical role in industrial control systems. A vulnerable control logic could lead to devastating consequences in the physical processes, as shown in Stuxnet and similar attacks. Over the years, academic and industrial researchers have investigated various fault injection and modification attacks on control logic as well as formal verification-based defenses. Although formal verification techniques have in general improved the quality of control logic programs, we find a significant gap between the academic research and the industry practices in defending against attacks on control logic. Besides, the future research directions remain unclear as to protect control logic from the ever-expanding attack surface partly caused by the increasing needs for interconnectivity.This work fills the gap by systematizing the knowledge of control logic modification attacks and the formal verificationbased defenses. Our study covers the full chain of developing and deploying control logic programs, from engineering stations to target PLC. The primary goals of the systematization are (1) to explore the evolving technology and security landscape surrounding control logic programs, (2) to investigate newly emerged attack surfaces on PLC systems and the formal verificationbased defenses, and (3) to identify the open challenges and needs that existing formal verification based-defenses failed to address. Based on the knowledge systematization, we provide a set of recommendations for both academic researchers and industry practitioners to better focus their work on countering critical and emerging threats.

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