Formal Architecture Specification for Time Analysis

Abstract

WCET calculus is nowadays a must for safety critical systems. As a matter of fact, basic real-time properties rely on accurate timings. Although over the last years, substantial progress has been made in order to get a more precise WCET, we believe that the design of the underlying frameworks deserve more attention. In this paper, we are concerned mainly with two aspects which deal with the modularity of these frameworks. First, we enhance the existing language Sim-nML for describing processors at the instruction level in order to capture modern architecture aspects. Second, we propose a light DSL in order to describe, in a formal prose, architectural aspects related to both the structural aspects as well as to the behavioral aspects.

Towards Formal Co-validation of Hardware and Software Timing Models of CPSs

“…Another approach is to extend classical ISA-level Architecture Description Languages (ADLs) [28], such as ArchC or Sim-nML, to include the specification of timing models at the micro-architecture level. The OTAWA WCET analysis framework relies on an extended Sim-nML to specify timing models of pipelines by describing resource allocations of instructions over pipeline stages, functional units and buffers [16]. In [24,25], the ADL Expression language is used to describe both ISA but also contention and parallelism relations at the microarchitecture, i.e.…”

Ensuring Consistency between Cycle-Accurate and Instruction Set Simulators

“…Architecture modeling for the real-time is not a new subject ( [HFC14], [CB13] provide a good overview). Traditional approaches are based on the use of Architecture Description Languages (ADLs) which allow the modeling of modern architectures, but do not have clear semantics.…”

“…More recently, [HFC14] gave formal semantics to an ADL tailored for timing analysis. This is done by means of constraint programming, allowing the use of constraint solvers to compute the WCET of basic blocks on complex architectures with out-of-order execution [HCFR13].…”

“…• Microarchitectural models used for pipeline simulation during WCET (Worst-Case Execution Time) analysis [HCFR13], [HFC14], [HRP17]. These models are used to compute safe over-approximations of the duration of a sequential piece of code, i.e., one function running without interruption on a processor core).…”