Formal hardware specification languages for protocol compliance verification

Bunker, A.S.; Gopalakrishnan, Ganesh; McKee, Sally A.

doi:10.1145/966137.966138

Cited by 22 publications

(16 citation statements)

References 50 publications

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“…Similar to C++ objects, modules allow related functionality and data to be incorporated into individual entities and to remain inaccessible by the other components of the system unless exposed explicitly. This allows modules to be developed independently and to be reused or sold in commercial libraries [8]. As an example, the skeleton of a SystemC module is presented in Listing 1: In this code fragment, SC_MODULE is one of SystemC's macros, which declares a C++ class named "Nand."…”

Section: Systemcmentioning

confidence: 99%

Optimized Temporal Monitors for SystemC

Tabakov

Vardi

2010

Runtime Verification

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SystemC is a modeling language built as an extension of C++. Its growing popularity and the increasing complexity of designs have motivated research efforts aimed at the verification of SystemC models using assertionbased verification (ABV), where the designer asserts properties that capture the design intent in a formal language such as PSL or SVA. The model then can be verified against the properties using runtime or formal verification techniques. In this paper we focus on automated generation of runtime monitors from temporal properties. Our focus is on minimizing runtime overhead, rather than monitor size or monitor-generation time. We identify four issues in monitor generation: state minimization, alphabet representation, alphabet minimization, and monitor encoding. We conduct extensive experimentation and identify a combination of settings that offers the best performance in terms of runtime overhead.

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Section: Systemcmentioning

confidence: 99%

Optimized Temporal Monitors for SystemC

Tabakov

Vardi

2010

Runtime Verification

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“…The same two models and the temporal properties described here are also used to evaluate empirically the performance of our proof-of-concept implementation 5 .…”

Section: A Exposing the Simulation Semanticsmentioning

confidence: 99%

“…notifc. // Suspend for a delta-cycle to allow all // computations to complete driver_event.notify(SC_ZERO_TIME); wait(driver_event); result.write(_a); } } void adder::do_add1() { wait(add1_activate_event); (_a) = (_a) + 1; addition_event.notify(); // immediate notification } A correct implementation of the Adder must satisfy the following property (using the syntax of [19]): 5 The source code of the models is online at http://www.cs.rice.edu/∼vardi/papers/memocode10.tar.bz2…”

Section: B Squaring Via Additionmentioning

confidence: 99%

“…The core language is built as a library extending C++ and provides macros for modeling the fundamental components of hardware and hybrid systems, for example, modules and channels. The object-oriented encapsulation of C++ and its inheritance capabilities help make designs modular, which in turn makes IP transfer and reuse easier [5]. Various libraries provide further functionality, for example, SystemC's Transaction-Level Modeling (TLM) library defines structures and protocols that streamline the development of high-level models.…”

Section: Introduction Systemcmentioning

confidence: 99%

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Monitoring temporal SystemC properties

Tabakov¹,

Vardi²

2010

Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)

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Abstract-Monitoring temporal SystemC properties is crucial for the validation of functional and transaction-level models, yet the current SystemC standard provides no support for temporal specifications. In this work we describe a temporal monitoring framework for the SystemC specification language defined by Tabakov et al. at FMCAD'08. Our framework uses a very minimal modification of the SystemC kernel, exposing event notifications and simulation phases. The user code is instrumented to allow observation of the relevant parts of the model state. As proof of concept, we use the framework to specify and check properties of two SystemC models. We show that monitoring SystemC properties using this framework has reasonable overhead (0.01% -1%) and has decreasing marginal cost. Finally, we demonstrate that monitoring at different levels of abstraction requires very small changes to the specification and the generated monitors. Based on our empirical results we argue that the additional expressive powers and flexibility of the framework does not incur a serious performance hit.

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“…Functional verification testbenches are typically written in domain-specific verification languages such as VHDL, Verilog, e or OpenVera [Bunker et al 2004;Engel and Spinczyk 2008], but may also include external data files or C routines [Yogesh et al 2009;Bergeron 2003]. The development of these testbenches is a software intensive process that has been reported by Bergeron to consume 70% of the total development time [Bergeron 2003], while in 2007, Li et al asserted that up to 80% of design costs in many circuit design projects are due to verification [Li et al 2007].…”

Section: Introductionmentioning

confidence: 99%

Model-driven automation for simulation-based functional verification

Linehan

O'Toole

Clarke

2012

ACM Trans. Des. Autom. Electron. Syst.

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Developing testbenches for dynamic functional verification of hardware designs is a software intensive process that lies on the critical path of electronic system design. The increasing capabilities of electronic components is contributing to the construction of complex verification environments that are increasingly difficult to understand, maintain, extend and reuse across projects. Modeldriven software engineering addresses issues of complexity, productivity and code quality through the use of high-level system models and subsequent automatic transformations. Reasoning about verification testbench decomposition becomes simpler at higher levels of abstraction. In particular, the aspect-oriented paradigm, when applied at the model level can minimize the overlap in functionality between modules, improving maintainability and reusability. This paper presents an aspect-oriented model-driven engineering process and toolset for the development of hardware verification testbenches. We illustrate how this process and toolset supports modularized design and automatic transformation to verification environment-specific models and source code through an industry case study.

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Formal hardware specification languages for protocol compliance verification

Cited by 22 publications

References 50 publications

Optimized Temporal Monitors for SystemC

Optimized Temporal Monitors for SystemC

Monitoring temporal SystemC properties

Model-driven automation for simulation-based functional verification

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