Formal Program Verification

Harton, Heather; Sitaraman, Murali; Krone, Joan

doi:10.1002/9780470050118.ecse331

Cited by 7 publications

(9 citation statements)

References 13 publications

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“…The proof rules that underlie VC generation and claims of soundness and completeness of those rules are discussed elsewhere [EHO94,HSK08,Hey95,Kro88,SWO97]. At present we are building and experimenting with two versions of the VC generator, one that begins with the goals of the implementation and proceeds to derive VCs one at a time by sweeping backward through the code, and another that leads to a table of known assertions and assertions to be proved and that is effectively neutral with respect to the order in which VCs are generated.…”

Section: Automated Generation Of Verification Conditionsmentioning

confidence: 99%

“…The formal proof rules underlying the goal-directed approach are discussed in [HSK08]. To illustrate the VCs generated by this approach, we have chosen benchmark #3 from [WSH08].…”

Section: Goal-directed Vc Generationmentioning

confidence: 99%

“…In addition to proving similar conditions, for code involving loops, VCs to prove the validity of the (programmer-supplied) loop invariant are also generated [HSK08]. In order to be able to illustrate the whole verification process through alternative methods, only simple examples have been discussed in this paper.…”

Section: Goal-directed Vc Generationmentioning

confidence: 99%

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Building a push-button RESOLVE verifier: Progress and challenges

et al. 2011

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A central objective of the verifying compiler grand challenge is to develop a push-button verifier that generates proofs of correctness in a syntax-driven fashion similar to the way an ordinary compiler generates machine code. The software developer’s role is then to provide suitable specifications and annotated code, but otherwise to have no direct involvement in the verification step. However, the general mathematical developments and results upon which software correctness is based may be established through a separate formal proof process in which proofs might be mechanically checked, but not necessarily automatically generated. While many ideas that could conceivably form the basis for software verification have been known “in principle” for decades, and several tools to support an aspect of verification have been devised, practical fully automated verification of full software behavior remains a grand challenge. This paper explains how RESOLVE takes a step towards addressing this challenge by integrating foundational and practical elements of software engineering, programming languages, and mathematical logic into a coherent framework. Current versions of the RESOLVE verifier generate verification conditions (VCs) for the correctness of component-based software in a modular fashion—one component at a time. The VCs are currently verified using automated capabilities of the Isabelle proof assistant, the SMT solver Z3, a minimalist rewrite prover, and some specialized decision procedures. Initial experiments with the tools and further analytic considerations show both the progress that has been made and the challenges that remain.

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Section: Automated Generation Of Verification Conditionsmentioning

confidence: 99%

“…The formal proof rules underlying the goal-directed approach are discussed in [HSK08]. To illustrate the VCs generated by this approach, we have chosen benchmark #3 from [WSH08].…”

Section: Goal-directed Vc Generationmentioning

confidence: 99%

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Building a push-button RESOLVE verifier: Progress and challenges

et al. 2011

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“…Educators may find RESOLVE overviews elsewhere [8] [9]. For an example, consider the specification of a Queue concept in which a queue ADT is modeled mathematically as a string of entries and primary operations to enqueue, dequeue, and find length are included.…”

Section: Engaging Studentsmentioning

confidence: 99%

Engaging students in specification and reasoning

Sitaraman

Hallstrom

White

et al. 2009

Proceedings of the 14th Annual ACM SIGCSE Conference on Innovation and Technology in Computer Science Education

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We introduce a "hands-on" experimentation approach for teaching mathematical specification and reasoning principles in a software engineering course. The approach is made possible by computer-aided analysis and reasoning tools that help achieve three central software engineering learning outcomes: (i) Learning to read specifications by creating test points using only specifications; (ii) Learning to use formal specifications in team software development while developing participating components independently; and (iii) Learning the connections between software and mathematical analysis by proving verification conditions that establish correctness for software components. Experimentation and evaluation results from two institutions show that our approach has had a positive impact.

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“…Every Integer variable is constrained to be within these bounds, and is initially 0. Verification Conditions: VCs are generated using a tool that implements the proof rules described in [26,27]. Briefly, there is a VC for each state in the program where the next statement involves establishing a precondition for the next operation, a loop invariant or progress metric, or the postcondition for the operation being verified.…”

Section: Input Specification and Code For Verificationmentioning

confidence: 99%

Incremental Benchmarks for Software Verification Tools and Techniques

Weide

Sitaraman

Harton

et al.

Verified Software: Theories, Tools, Experiments

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Abstract. This paper proposes an initial catalog of easy-to-state, relatively simple, and incrementally more and more challenging benchmark problems for the Verified Software Initiative. These benchmarks support assessment of verification tools and techniques to prove total correctness of functionality of sequential object-based and object-oriented software. The problems are designed to help evaluate the state-of-the-art and the pace of progress toward verified software in the near term, and in this sense, they are just the beginning. They will allow researchers to illustrate and explain how proposed tools and techniques deal with known pitfalls and well-understood issues, as well as how they can be used to discover and attack new ones. Unlike currently available benchmarks based on "real-world" software systems, the proposed challenge problems are expected to be amenable to "push-button" verification that leverages current technology.

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Formal Program Verification

Cited by 7 publications

References 13 publications

Building a push-button RESOLVE verifier: Progress and challenges

Building a push-button RESOLVE verifier: Progress and challenges

Engaging students in specification and reasoning

Incremental Benchmarks for Software Verification Tools and Techniques

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