2017
DOI: 10.3390/systems5010017
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Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture

Abstract: Abstract:Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC) design. To achieve this, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in the validation process. The Event-B method is a promising formal approach that can be used to develop, model and prov… Show more

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Cited by 3 publications
(1 citation statement)
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“…The role of the router is to forward packets to their next destination. The proposed router [25,26] (as shown in Figure 2) consists of 4 blocks for each direction: North, South, East and West, plus an additional block (local port) which connects the router with a Processing Element (PE) (computing unit). Each block contains 2 sub-blocks.…”
Section: Routermentioning
confidence: 99%
“…The role of the router is to forward packets to their next destination. The proposed router [25,26] (as shown in Figure 2) consists of 4 blocks for each direction: North, South, East and West, plus an additional block (local port) which connects the router with a Processing Element (PE) (computing unit). Each block contains 2 sub-blocks.…”
Section: Routermentioning
confidence: 99%