Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

Abstract

We propose to utilize a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimization is then conducted using Cartesian Genetic Programming (CGP) which utilizes a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8% on average with respect to results of the conventional SIS tool.

Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

“…The fitness calculation is computationally very intensive, since the number of test vectors grows exponentially with the number of primary inputs. Recently, it has been sped up by applying parallelism at various levels (data, thread, process) [27] or by introducing formal methods based on, for example, SAT solving [28].…”

Cartesian genetic programming as local optimizer of logic networks

“…In order to optimize complex circuits, the fitness function was later redesigned to perform functional equivalence checking by means of a SAT solver instead of testing all possible input combinations [7]. This method led to a 25% area improvement with respect to the circuits heavily optimized by ABC [10].…”

“…Since the satisfiability (SAT) solvers were significantly improved during last few years, the SAT-based equivalence checking was included into CGP and implemented in [7]. The idea is to create an auxiliary circuit H which is composed of the circuits to be checked (circuit G and candidate circuit) and a set of XOR gates connected to the corresponding outputs of the circuits to be checked.…”

“…In order to perform unconstrained and unbiased circuit optimization and find more compact circuit implementations, evolutionary logic synthesis and optimization methods were introduced in recent years [6], [7], [8]. For the cost of runtime, evolutionary algorithms were able to improve some results of conventional synthesis methods.…”

“…As CGP is intended to iteratively optimize small, randomly chosen subcircuits, the scalability problems known from the CGPbased circuit evolution will be eliminated. This work should be understood as a complementary approach to the already existing CGP-based global optimization methods developed for combinational circuits [7], [10].…”