Formal verification of characteristic properties

Allemand, Michel

doi:10.1007/3-540-59047-1_56

Cited by 1 publication

(1 citation statement)

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“…First order logic based theorem provers such as Boyer's and Moore's NQTHM [28,17,29], or the Larch Prover [1] have been used for years to handle parametric designs, as well as several higher order logic systems like HOL [14,8,27], VER.ITAS [16], or NUPRL [10,4], and there are studies which compare both approaches [2]. In all of them, verification becomes an activity bound to interactive, computer assisted theorem proving.…”

Section: Related Workmentioning

confidence: 99%

Fully automatic verification and error detection for parameterized iterative sequential circuits

Margaria

1996

Tools and Algorithms for the Construction and Analysis of Systems

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The paper shows how iterative parametric sequential circuits, which are most relevant in practice, can be verified fully automatically. Key observation is that monadic second-order logic on strings provides an adequate level for hardware specification and implementation. This allows us to apply the corresponding decision procedure and counter-model generator implemented in the Mona verification tool, which, for the first time, yields 'push-button' verification, and error detection and diagnosis for the considered class of circuits. As illustrated by means of various versions of counters, this approach captures hierarchical and mixed mode verification, as well as the treatment of varying connectivity in iterative designs. MotivationA clear trend towards reuse of existing designs is the emergence of parametric designs in standard libraries [13]. While such "families of circuits" have been already popular in the hardware verification community for years, where they are the best examples for induction-based reasoning in the hardware application domain, industrial practice did not feature parametric designs in standard libraries because of lack of consolidated methods for their lull-automatic treatment in the design lifecycle. Thus the pressure towards fully automated methods for the analysis, verification, and fault detection of parametric circuits and their specifications grows with the increasing demand for design reuse. Unfortunately, the standard automata theoretic techniques of the hardware community fail here, because the treatment of automata of unbounded size is required. At this stage, Basin and Klarlund discovered that monadic second-order logic on strings, although 'hopeless' from the complexity point of view, is well-behaved in many practical applications, and, in particular, well-suited for the fully automatic verification of *Fakult~t f'dr Mathematik und Informatik, Universitiit Passau, Innstr. 33, 94032 Passau (D), tel: +49 851 509.3096, fax: +49 851 509.3092, ~iziana@fmi.tmi-paasau.dl

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Section: Related Workmentioning

confidence: 99%

Fully automatic verification and error detection for parameterized iterative sequential circuits

Margaria

1996

Tools and Algorithms for the Construction and Analysis of Systems

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Formal verification of characteristic properties

Cited by 1 publication

References 3 publications

Fully automatic verification and error detection for parameterized iterative sequential circuits

Fully automatic verification and error detection for parameterized iterative sequential circuits

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