Formal verification of code motion techniques using data-flow-driven equivalence checking

Abstract

A formal verification method for checking correctness of code motion techniques is presented in this article. Finite State Machine with Datapath (FSMD) models have been used to represent the input and the output behaviors of each synthesis step. The method introduces cutpoints in one FSMD, visualizes its computations as concatenation of paths from cutpoints to cutpoints, and then identifies equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. Unlike many other reported techniques, the method is capable of verifying both uniform and nonuniform code motion techniques. It has been underlined in this work that for nonuniform code motions, identifying equivalent path segments involves model checking of some data-flow properties. Our method automatically identifies the situations where such properties are needed to be checked during equivalence checking, generates the appropriate properties, and invokes the model checking tool NuSMV to verify them. The correctness and the complexity of the method have been dealt with. Experimental results demonstrate the effectiveness of the method.

Counter‐example generation procedure for path‐based equivalence checkers

“…The work reported in [10] improves the equivalence checking method of [4] to deal with code transformations employing speculation and global common sub-expression extraction. The enhanced method of [4] presented in [11] can handle both uniform and non-uniform code motions applied during the scheduling phase of HLS. All these methods [3,4,[9][10][11] cannot handle code motions across loops.…”

“…Many path-based approaches have been proposed for verification of HLS [3,4,7,[9][10][11][12][13][14][15], where each behaviour is represented by a finite state machine with datapath (FSMD) [16]. In general, path-based approaches decompose each FSMD into a finite set of finite paths and the equivalence of FSMDs is established by showing path level equivalence between two FSMDs.…”

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

“…The aim of the formal verification is to prove design correctness using mathematical certainty, which divided into three categories: equivalence checking, model checking and theory proven. Equivalence checking [11] is used to prove that the two design models have the same function, which is actually the most widely used formal verification technology, such as Cadence's Conformal and Synopsys's Formality. Model checking [12,13] is used to prove that a design meets certain attributes, such as Cadence's Formal Checker.…”

A Scheme for Automated Evaluation of Programming Assignments using FSMD based Equivalence Checking

“…In this work, we have chosen the FSMD model to represent the programs since equivalence checking of FSMDs is a well studied problem and has found extensive application in translation validation of programs [5,7,8,4,2,3]. Specifically, FSMD based equivalence checking is first proposed in [5], which is later developed to handle uniform and nonuniform code motion based optimization techniques in [7,8,4].…”

“…Specifically, FSMD based equivalence checking is first proposed in [5], which is later developed to handle uniform and nonuniform code motion based optimization techniques in [7,8,4]. This method is general enough for checking equivalence of digital circuits as well [6].…”