Formal Verification of Peephole Optimizations in Asynchronous Circuits

Abstract

This paper proposes and applies novel techniques for formal verification of peephole optimizations in asynchronous circuits. We verify whether locally optimized modules can replace parts of an existing circuit under assumptions regarding the operation of the optimized modules in context. A verification rule related to assume-guarantee and hierarchical verification is presented, using relative timing constraints as optimization assumptions. We present the verification of speed-optimizations in an asynchronous arbiter as a case study.