Formal verification of UML-modeled machine controls

Klotz, Thomas; Fordran, Eva; Straube, Bernd; Haufe, Jürgen

doi:10.1109/etfa.2009.5347044

Cited by 16 publications

(11 citation statements)

References 17 publications

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“…Furthermore model checking, which is an automated method for verifying a model against a set of requirements, is available. As of yet this method [8] is only suitable for discrete model components and is therefore used in the formal verification of the control model's UML statechart. After successful verification a validated and verified PLC program based on the IEC 61131-3 standard can be generated automatically from the control model.…”

Section: Figure 2 Conformity Of Simulation and Realtime Resultsmentioning

confidence: 99%

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Modelling the real-time behaviour of machine controls using UML statecharts

Seidel

Klotz

Donath

et al. 2010

2010 IEEE 15th Conference on Emerging Technologies &Amp; Factory Automation (ETFA 2010)

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For covering the real-time characteristics of an automation system during model-based design it is essential to model not only the function but also the behaviour of the control programs running on a real-time controller. This paper introduces an approach to the modelling and evaluation of the functional and time behaviour of Programmable Logic Controllers (PLC) on model level. The control algorithm consisting of UML statecharts is extended with an execution model of the controller which is also given as a statechart. The approach is integrated into a model-based design system for industrial control systems focusing on the field of production systems. An example will be employed to illustrate the benefits of a model-based design system which does incorporate realtime aspects of the controller

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Section: Figure 2 Conformity Of Simulation and Realtime Resultsmentioning

confidence: 99%

“…The execution model will be of use both in the simulation and formal verification [8] of machine controls. It is an important benefit of describing execution models with statecharts that the statechart level is applied throughout the model.…”

Section: Application and Future Workmentioning

confidence: 99%

Modelling the real-time behaviour of machine controls using UML statecharts

Seidel

Klotz

Donath

et al. 2010

2010 IEEE 15th Conference on Emerging Technologies &Amp; Factory Automation (ETFA 2010)

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“…Sacha [98] defined finite state time machines and use it as an intermediate format in conversion between state machine diagrams and UPPAAL models. Klotz et al [64] also use UML state chart models and transform them to NuSMV models in verification of a case filling machine. They were able to verify basic liveness and safety properties in around 80 s for a system model with three state charts.…”

Section: Other Approaches That Use Model Checkingmentioning

confidence: 99%

An overview of model checking practices on verification of PLC software

et al. 2014

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Programmable logic controllers (PLCs) are heavily used in industrial control systems, because of their high capacity of simultaneous input/output processing capabilities. Characteristically, PLC systems are used in mission critical systems, and PLC software needs to conform real-time constraints in order to work properly. Since PLC programming requires mastering low-level instructions or assembly like languages, an important step in PLC software production is modelling using a formal approach like Petri nets or automata. Afterward, PLC software is produced semiautomatically from the model and refined iteratively. Model checking, on the other hand, is a well-known software verification approach, where typically a set of timed properties are verified by exploring the transition system produced from the software model at hand. Naturally, model checking is applied in a variety of ways to verify the correctness of PLC-based software. In this paper, we provide a broad view about the difficulties that are encountered during the model checking process applied at the verification phase of PLC software production. We classify the approaches from two different perCommunicated by Prof. Einar Broch Johnsen and Luigia Petre. spectives: first, the model checking approach/tool used in the verification process, and second, the software model/source code and its transformation to model checker's specification language. In a nutshell, we have mainly examined SPIN, SMV, and UPPAAL-based model checking activities and model construction using Instruction Lists (and alike), Function Block Diagrams, and Petri nets/automata-based model construction activities. As a result of our studies, we provide a comparison among the studies in the literature regarding various aspects like their application areas, performance considerations, and model checking processes. Our survey can be used to provide guidance for the scholars and practitioners planning to integrate model checking to PLC-based software verification activities.

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“…The given input and internal variables may trigger events to fire transitions; only the event firing the transition with the highest priority is taken into account, and all others are rejected, i.e., there is no event queue. For a detailed presentation of this subset readers should refer to [18].…”

Section: B Modeling and Verification Using Uml Statechartsmentioning

confidence: 99%

Reliable execution of statechart-generated correct embedded software under soft errors

Ferreira

Klotz

Vörtler

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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This paper proposes a design methodology for faulttolerant embedded systems development that starts from software specification and goes down to hardware execution. The proposed design methodology uses formally verified and correctby-construction software created from high-level UML statechart models for software specification and implementation. On the hardware reliability side, this paper uses the MoMa architecture for reliable embedded computing which we deploy as a softcore onto an off-the-shelf FPGA. MoMa introduces architectural innovations that support the semantics of the UML statechart execution in a reliable fashion. The proposed design methodology is evaluated with a real automotive case study based on an exhaustive FPGA-implemented fault injection campaign

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Formal verification of UML-modeled machine controls

Cited by 16 publications

References 17 publications

Modelling the real-time behaviour of machine controls using UML statecharts

Modelling the real-time behaviour of machine controls using UML statecharts

An overview of model checking practices on verification of PLC software

Reliable execution of statechart-generated correct embedded software under soft errors

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