Formation of Shallow Junctions by HCl-Based Si Etch Followed by Selective Epitaxy of B-Doped Si[sub 1−x]Ge[sub x] in RPCVD

Abstract

Formation of shallow source/drain junctions by using HCl-based Si etch followed by selective deposition of in situ heavily B-doped SiGe in a reduced pressure chemical vapor deposition reactor is presented. The etching parameters were optimized to obtain a smooth surface prior to deposition of the SiGe layers. In the epitaxy process, SiGe layers with a resistivity of 5 ϫ 10 Ϫ4 ⍀ cm were obtained by tuning the partial pressure of the B and Ge precursors. A problem with selectivity in the epitaxy step was encountered when combing the etch and growth processes, but a practical solution is presented. Integration issues such as loading effect, pile-up, and defect generation have also been investigated.

In situ HCl etching of Si for the elaboration of locally misorientated surfaces

“…Impact of the temperature on the formation of facets during the in situ HCl etching of Si A limited number of studies have dealt with the in situ HCl chemical vapour etching (CVE) of bulk Si(1 0 0). The etch pressure was either 40 Torr [21,22] or 20 Torr [23]. Meanwhile, the etch temperature was either equal to 850 8C [21], inbetween 770 8C and 900 8C [23] or in the 800-1150 8C range [24].…”

“…The etch pressure was either 40 Torr [21,22] or 20 Torr [23]. Meanwhile, the etch temperature was either equal to 850 8C [21], inbetween 770 8C and 900 8C [23] or in the 800-1150 8C range [24]. The main advantage of the in situ HCl etching compared to a more conventional plasma dry etching lies in the formation of facets with up to 68 misorientation angles.…”

“…This effect, already reported in the literature (see Refs. [17,21,23]), is akin to the global ''loading'' effect observed during the selective epitaxial growth of SiGe on patterned wafers (see Ref. [25]).…”

Application of selective epitaxy for formation of ultra shallow SiGe-based junctions

“…We would like to mention here that there is a pile-up at the edges of SiGe layer in Fig. 2a, which usually appears in SEG due to the distribution of the growth rate in the oxide openings [12].…”

Inspection of defects and metallic contamination in SiGe:B CMOS using an in-line photoluminescence monitor

“…Typical challenges include: Maintaining SiGe growth uniformity, minimizing effects of global and local loading, sustaining or relaxing strain in a controllable fashion, and preventing uncontrolled formation of defects, precipitation of dopants, and contamination. [4][5] Process induced defects and contamination deteriorate device characteristics through increased junction leakage, surface roughening, impaired oxide breakdown voltage, and/or threshold voltage fluctuations leading to reduced device yield. [6][7][8][9][10][11] Successful integration of the SiGe process with CMOS technology will be heavily dependent on overcoming these challenges and sustaining the process in acceptable control limits.…”