Formation of silicon-on-insulator layer with midair cavity for meniscus force-mediated layer transfer and high-performance transistor fabrication on glass

Abstract

We attempted to transfer a phosphorus ion (P + )-implanted oxidized silicon-on-insulator (SOI) layer with a midair cavity to a glass substrate using meniscus force at a low temperature. The SiO 2 column size was controlled by etching time and the minimum column size was 104 nm. The transfer yield of the implanted sample was significantly improved by decreasing the column size, and the maximum transfer yield was 95% when the implantation dose was 1 ' 10 15 cm %2 . The causes of increasing transfer yield are considered to be the tapered SiO 2 column shape and the hydrophilicity of the surface of oxidized samples with implantation. N-channel thin-film transistors (TFTs) fabricated using the films on glass at 300°C showed a field-effect mobility of 505 cm 2 V %1 s %1 , a threshold voltage of 2.47 V and a subthreshold swing of 324 mV/dec. on average.

Single-Crystalline Si-CMOS Circuit Fabrication on Polyethylene Terephthalate Substrate by Meniscus Force-Mediated Layer Transfer

“…The tapered side-wall structure of an SiO 2 pillar, as shown in Fig. 2(b), was formed by the conventional phosphorus I/I (P + : 1 × 10 15 cm −2 , 50 keV) for the formation of the n-channels S/D with a concentration peak at the SOI/BOX layer interface, which increases the etching rate of the upper BOX layer [28]. However, controlling the pillar shape for p-channel sc-Si islands is more difficult owing to the varying I/I conditions.…”