Formation process of high-purity Ge-on-insulator layers by Ge-condensation technique

Nakaharai, Shu; Tezuka, T.; Hirashita, N.; Toyoda, Eiji; Moriyama, Yoshihiko; Sugiyama, N.; Takagi, Shinichi

doi:10.1063/1.3068339

Cited by 49 publications

(37 citation statements)

References 27 publications

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“…Fig. 5 shows TEM photographs of an ultrathin GOI structure with GOI thickness of 2 nm to 25 nm, which confirms that the GOI thickness can be precisely controlled by changing the amount of Ge before the condensation [7]. The residual Si concentration is estimated to be less than 0.01 % by SIMS analyses, meaning the high purity of the fabricated structures.…”

Section: Introductionsupporting

confidence: 60%

Mobility-Enhanced Device Technologies Using SiGe/Ge MOS Channels

et al. 2007

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Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on the development of mobilityenhanced CMOS device structures using strained-Si/SiGe/Ge MOS channels and the carrier transport properties in those channels. It is shown, particularly, that uniaxial compressive strain and Ge channels are quite effective in pMOS performance enhancement, while uniaxial tensile strain is effective in nMOS performance.

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Section: Introductionsupporting

confidence: 60%

Mobility-Enhanced Device Technologies Using SiGe/Ge MOS Channels

et al. 2007

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“…Thus, another difficult challenge in Ge CMOS is to form thin and high quality Ge films on Si substrates. As for the formation of Ge thin films on Si substrates, we have already proposed the Ge condensation technique [35][36][37], which is a method to from GO[ structures by simply oxidizing SiGe layers epitaxially-grown on SOl substrates. The schematic process flow is shown in Fig.ll. We have reported GOI p-MOSFETs fabricated on a lSO mm GOI substrate, exhibiting the 3.1 time higher hole mobility than the Si universal hole mobility [38].…”

Section: I-lno53gao47as(100nm)mentioning

confidence: 99%

High mobility channel MOS device technologies toward nano-CMOS era

Takagi

2011

2011 IEEE Nanotechnology Materials and Devices Conference

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MOSFETs using channel materials with high mobility and low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to SiGe, Ge and llI-V channels. Thus, CMOS family utilizing llI-V/Ge channels on Si substrates can be key devices for high performance and low power advanced LSIs in the future. In this paper, possible solutions for realizing llI-V/Ge MOSFETs on the Si platform are presented with an emphasis on CMOS integration of llI-V and Ge MOSFETs as ultra-thin body channels, which is mandatory for scaled CMOS. The high quality III-V channel formation on Si substrates can be realized through direct wafer bonding. The gate stack formation, which is also a critical issue for llI-V/Ge CMOS integration, is constructed on a basis of atomic layer deposition (ALD) AI203 gate insulators for both InGaAs and Ge MOSFETs. Another important concern in the integration process of llI-V and Ge MOSFETs is source/drain (SID) formation. Ni-based metal SID technologies are implemented for both InGaAs and Ge MOSFETs. By combining these technologies, we demonstrate successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

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“…We considered that it was selective oxidation of Si due to the energetic stability of SiO 2 , which was similar to the case of Ge condensation. 32 Si reacted with oxygen in Fe NCs at the interfaces selectively, and using this reaction energy, Fe diffusion occurred. This mechanism can also be applied to our Fe NCs.…”

Section: Reaction Of Crystal-orientation-controlled Fe Ncs On Si mentioning

confidence: 99%

Influence of nanometer-sized interface on reaction of iron nanocrystals epitaxially grown on silicon substrates with oxygen gas

Hamanaka

Nakamura

Ishibe

et al. 2013

Journal of Applied Physics

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Iron (Fe) nanocrystals (NCs) were epitaxially grown on silicon (Si) substrates, where interfacial alloying of Fe and Si (silicidation) was prevented using an ultrathin SiO2 film. Nanowindows (NWs) composed of Si and germanium (Ge) were introduced into this SiO2 layer. The crystallographic arrangement of the Si substrates was conveyed though the NWs, while Fe and Si atoms were not intermixed. Reactions between the epitaxial Fe NCs and Si substrate in the presence of oxygen gas were also investigated. Oxygen atoms facilitated the diffusion of Fe from NCs to Si substrates mainly through Si NWs. As a result, increase of oxygen concentration led to Si oxidation near the interface. This means Fe NCs played a role like a catalysis for Si oxidation. The interfacial reaction was changed drastically by control of nanometer-sized interfaces using Ge NWs in the ultrathin SiO2 films.

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Formation process of high-purity Ge-on-insulator layers by Ge-condensation technique

Cited by 49 publications

References 27 publications

Mobility-Enhanced Device Technologies Using SiGe/Ge MOS Channels

Mobility-Enhanced Device Technologies Using SiGe/Ge MOS Channels

High mobility channel MOS device technologies toward nano-CMOS era

Influence of nanometer-sized interface on reaction of iron nanocrystals epitaxially grown on silicon substrates with oxygen gas

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