Forty-three ways of systolic matrix multiplication

Milovanovic, Igor Z.; Bekakos, M. P.; Tselepis, I. N.; Milovanovic, Emina I.

doi:10.1080/00207160802275944

Cited by 3 publications

(4 citation statements)

References 14 publications

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“…Also, the execution time of the array should be as small as possible for the given number of PEs. This requires substantial modification of the systolic array synthesis procedure described so far in the literature [3][4][5][6][7].…”

Section: Problem Definitionmentioning

confidence: 99%

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Hexagonal arrays for fault-tolerant matrix multiplication

Milovanovic

Stojcev

2015

Filomat

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This paper describes mathematical procedure for designing hexagonal systolic arrays that implement fault-tolerant matrix multiplication. Fault-tolerance is achieved by introducing redundancy at algorithm level by defining three equivalent algorithms with disjoint index spaces. The essence of the proposed method is based on mapping data dependency graph that corresponds to the matrix multiplication algorithm, by an appropriate epimorphism, into a graph with desired properties. Since there is a 1:1 correspondence between the algorithm and it?s graph representation, all transformations performed on the graph directly affect the algorithm. Chosen epimorphism depends on the projection direction vector ?? = [?1 ?2 ?3]T and enables obtaining hexagonal arrays with optimal number of processing elements (PEs) for the given matrix dimensions, which realizes fault-tolerant matrix multiplication for the shortest possible time for that number of PEs. The proposed procedure is formally described by explicit formulas and can be used as a software tool for automatic synthesis of fault-tolerant arrays.

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Section: Problem Definitionmentioning

confidence: 99%

“…In [4] hexagonal SA with optimal number of PEs which computes matrix product was synthesized for the direction µ…”

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confidence: 99%

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Hexagonal arrays for fault-tolerant matrix multiplication

Milovanovic

Stojcev

2015

Filomat

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“…Minimizing the communication cost has been studied thoroughly in the past both at the architectural and the algorithmic levels. From an architectural perspective, three main parallel architectures have been developed to boost the computer performance: shared memory [6], [7], distributed memory [8], [9] and systolic array [10], [11]. For the shared memory architecture, the communication cost is mostly a consequence of the data movement throughout the memory hierarchy.…”

Section: Introductionmentioning

confidence: 99%

Parallel matrix multiplication on memristor-based computation-in-memory architecture

Haron

Nane

et al. 2016

2016 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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One of the most important constraints of today's architectures for data-intensive applications is the limited bandwidth due to the memory-processor communication bottleneck. This significantly impacts performance and energy. For instance, the energy consumption share of communication and memory access may exceed 80%. Recently, the concept of Computation-in-Memory (CIM) was proposed, which is based on the integration of storage and computation in the same physical location using a crossbar topology and non-volatile resistive-switching memristor technology. To illustrate the tremendous potential of CIM architecture in exploiting massively parallel computation while reducing the communication overhead, we present a communicationefficient mapping of a large-scale matrix multiplication algorithm on the CIM architecture. The experimental results show that, depending on the matrix size, CIM architecture exhibits several orders of magnitude higher performance in total execution time and two orders of magnitude better in total energy consumption than the multicore-based on the shared memory architecture.

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