Forward error correction for high-speed I/O

Narasimha, Rajan; Shanbhag, Naresh R.

doi:10.1109/acssc.2008.5074674

Cited by 11 publications

(9 citation statements)

References 7 publications

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“…The measurement results provide a quantitative assessment of how coding gain affects the trade-off between transmit swing, jitter tolerance, BER and power. We show that much of the promise of FEC identified in [4,5] can indeed be fulfilled in practice.…”

Section: Introductionmentioning

confidence: 87%

“…The encoder and decoder have a 16-way parallel architecture, which makes the core clock frequency 1/16 th of the line rate, and effects an intrinsic interleaving function for free, thereby compensating for burst errors [4]. The encoder and decoder can be bypassed to allow for uncoded transmission ( 1), in order to enable comparison with conventional transceivers.…”

Section: B Transceiver Overviewmentioning

confidence: 99%

“…We previously studied the application of FEC to 10 Gb/s signaling over channels with 12 to 15 dB loss at Nyquist via analysis and simulations, and concluded that binary BCH codes along with receive equalization provides a coding gain of 3 to 6 dB at a BER of 10 -15 [4,5]. The reduced SNR requirements represented by the coding gain may be employed to: (a) reduce transmit swing, (b) reduce equalizer complexity, (c) enhance jitter-tolerance, and (d) improve comparator offset tolerance.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

FEC-based 4 Gb/s backplane transceiver in 90nm CMOS

Faust

Narasimha

Bhatia

et al. 2012

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

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This paper presents the first reported design of a forward error correction (FEC)-based high-speed serial link. A 4 Gb/s line rate transceiver in 90nm CMOS is designed with short block length BCH codes. FEC is shown to be effective for high code rates, high information rates and low SNR channels. Measurement results of the transceiver over a 18.2 dB Nyquist loss channel show a reduction in minimum BER, and an increase in jitter tolerance at low transmit swings. For a BER 10 -12 , the addition of FEC reduces the required transmit signal swing, from approximately 0.75 V ppd to less than 0.5 V ppd .

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Section: Introductionmentioning

confidence: 87%

Section: B Transceiver Overviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

FEC-based 4 Gb/s backplane transceiver in 90nm CMOS

Faust

Narasimha

Bhatia

et al. 2012

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

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“…In this paper, we carry forward the work presented in [6] and examine how FEC with 2-PAM and 4-PAM modulations impacts the design budgets in a high speed serial link. In particular, we examine how the component-level budgets for transmitter, receiver amplifier, ADC, clock generation and recovery units and comparator (decision device) can be relaxed, by expending FEC power.…”

Section: Introductionmentioning

confidence: 98%

“…The model just described is used to compute preFEC-BER, BER pre . In the design phase, where to goal is to get a quick hold of the component budgets, the postFEC-BER, BER post , is computed from BER pre assuming that the effect of correlated errors can be handled by interleaving, without a power penalty [6]. For example, a DFE produces statistically significant burst errors of burst length equal to the DFE length (L d ).…”

Section: Introductionmentioning

confidence: 99%