Forward Error Correction via Channel Coding

Gazi, Orhan

doi:10.1007/978-3-030-33380-5

Cited by 12 publications

(7 citation statements)

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“…As the 't' bit increases, the chip area and Power of the BCH designs will also increase. The BCH-ED (15,5,3) for TEC utilizes more clock cycles and Power due to the advanced decoding mechanism. As the 't' bit increases, the Throughput and hardware efficiency will be decreased drastically.…”

Section: Resultsmentioning

confidence: 99%

“…Where the polynomial of the received codeword is r(x) = 𝑟 0 + 𝑟 1 x + 𝑟 2 x 2 + ⋯ + 𝑟 𝑛−1 x 𝑛−1 and error input is e(x) = 𝑒 0 + 𝑒 1 x + 𝑒 2 x 2 + ⋯ + 𝑒 𝑛−1 x 𝑛−1 . The syndrome (Si) is calculated [28] using (5). The syndrome is calculated for SEC operation is represented using (6).…”

Section: Syndrome Calculationmentioning

confidence: 99%

“…The decoding mechanism of the BCH codes is easily designed using the syndrome decoding approach. The BCH codes used many applications, including solidstate drives, cryptography, disk drives, compact disc players, flash drives, and bar codes [4], [5]. The subclass of the BCH code is narrow-sense primitive-based BCH codes and is known to improve performance metrics using features like minimum distance and dimensions [6].…”

Section: Introductionmentioning

confidence: 99%

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An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

Puttaraju,

Muniyappa

2024

IJEECS

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The bose-chaudhuri-hocquenghem (BCH) codes are a cyclic error correction codes (ECC) class. The BCH is constructed by using a polynomial over the Galois field. The BCH codes can detect and correct the multi-bits with an easy decoding mechanism. The BCH codes are used in most of the storage device's cryptography, disk drives, and satellite applications. This manuscript presents an efficient high-throughput BCH module with an encoding and decoding mechanism for multi-bit corrections. The BCH code of (15, k) is used to construct the encoder and decoder architectures. The BCH encoder decoder (ED) module with single error correction (SEC), double error correction (DEC), and triple-error correction (TEC) are discussed in detail. The BCH encoder module uses a linear feedback shift register (LFSR). The BCH decoder with SEC and DEC is constructed using the syndrome generator module (SGM) and chien search module (CSM). The BCH decoder with TEC is designed using SGM, inversion-based berlekamp-massey-algorithm (BMA), and CSMs. The BCH-ED module with SEC, DEC, and TEC utilizes <1 % chip area on Artix-7 FPGA. The BCH-ED with SEC, DEC, and TEC achieves a throughput of 7.13 Gbps, 1.2 Gbps, and 0.803 Gbps, respectively. Lastly, the BCH module is compared with existing BCH approaches with better improvement in chip area, frequency, and throughput parameters.

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Section: Resultsmentioning

confidence: 99%

Section: Syndrome Calculationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

Puttaraju,

Muniyappa

2024

IJEECS

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“…The quality of a digital transmission depends mainly on the quantity of errors introduced into the transmission channel [1] [2]. Error checking by coding is therefore essential.…”

Section: Introductionmentioning

confidence: 99%

Performance Comparison of New Designs of Chien Search and Syndrome Blocks for BCH and Reed Solomon Codes

Elghayyaty

Mouhib

Wahbi

et al. 2022

Int. j. commun. netw. inf. secur.

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Error correcting codes constitute one of the core technologies in telecommunications field, especially digital communication applications. The objective of this paper is to compare performance among new designs of chien search block on the one hand and syndrome architectures on the other hand in error correcting codes. All comparison of all designs is made by computing the number of logic, bit error rate values and number of iteration in the case of syndrome architectures Analysis results show that the performances of the new designs based on both second factorization method and Three-Parallel Syndrome architecture are superior to the performances of traditional designs.

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“…Error-correcting coding is very important mean to provide the reliable data communication [1][2][3]. For the last 20 years, significant attention was paid to investigating of low-density parity-check (LDPC) codes.…”

Section: Introductionmentioning

confidence: 99%

Decoding of linear codes for single error bursts correction based on the determination of certain events

Ovchinnikov

Veresova

Fominykh

2022

ICS

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Introduction: In modern systems for communication, data storage and processing the error-correction capability of codes are estimated for memoryless channels. In real channels the noise is correlated, which leads to grouping error in bursts. A traditional method to fight this phenomenon is channel decorrelation, which does not allow developing of coding schemes, mostly utilizing the channel capacity. Thus the development of bursts decoding algorithms for arbitrary linear codes is the actual task. Purpose: To develop a single error burst decoding algorithm for linear codes, to estimate the decoding error probability and computational complexity. Results: Two approaches are proposed to burst error correction. The first one is based on combining the window sliding modification of well-known bit-flipping algorithm with preliminary analysis of the structure of parity check matrix. The second one is based on the recursive procedure of constructing the sequence of certain events which, in the worst case, performs the exhaustive search of error bursts, but in many cases the search may be significantly decreased by using the proposed heuristics. The proposed recursive decoding algorithm allows a guaranteed correction of any single error bursts within burst-correction capability of the code, and in many cases beyond the burst-correction capability. The complexity of this algorithm is significantly lower than that of a bit flipping algorithm if the parity-check matrix of the code is sparse enough. An alternative hybrid decoding algorithm is proposed utilizing the bit-flipping approach and showing the error probability and completion time comparable to the recursive algorithm, however, in this case the possibility of a guaranteed burst correction hardly can be proved. Practical relevance: The proposed decoding methods may be used in modern and perspective communication systems, allowing energy saving and increasing reliability of data transmission by better error performance and computational complexity.

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Forward Error Correction via Channel Coding

Cited by 12 publications

References 0 publications

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

Performance Comparison of New Designs of Chien Search and Syndrome Blocks for BCH and Reed Solomon Codes

Decoding of linear codes for single error bursts correction based on the determination of certain events

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