Forward model checking techniques oriented to buggy designs

Iwashita,; Nakata,

doi:10.1109/iccad.1997.643567

Cited by 29 publications

(15 citation statements)

References 9 publications

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“…In practice, forward traversal usually is much faster [17,54,57,58]. The reason may be that unreachable states do not have to be visited and BDDs behave much better.…”

Section: Model Checkingmentioning

confidence: 99%

A survey of recent advances in SAT-based formal verification

Prasad

Biere

Gupta³

2005

Int J Softw Tools Technol Transfer

205

120

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Abstract. Dramatic improvements in SAT solver technology over the last decade and the growing need for more efficient and scalable verification solutions have fueled research in verification methods based on SAT solvers. This paper presents a survey of the latest developments in SAT-based formal verification, including incomplete methods such as bounded model checking and complete methods for model checking. We focus on how the surveyed techniques formulate the verification problem as a SAT problem and how they exploit crucial aspects of a SAT solver, such as application-specific heuristics and conflict-driven learning. Finally, we summarize the noteworthy achievements in this area so far and note the major challenges in making this technology more pervasive in industrial design verification flows.

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“…In practice, forward traversal usually is much faster [17,54,57,58]. The reason may be that unreachable states do not have to be visited and BDDs behave much better.…”

Section: Model Checkingmentioning

confidence: 99%

A survey of recent advances in SAT-based formal verification

Prasad

Biere

Gupta³

2005

Int J Softw Tools Technol Transfer

205

120

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“…The technique performs forward image computation for state traversal, a characteristic shared by forward model checking [6]. Experimental results [2] show that this approach outperforms other property checking methods for certain classes of systems and properties.…”

Section: Bounded Property Checkingmentioning

confidence: 99%

Dynamic guiding of bounded property checking

Peranandam

Weiß

Ruf

et al. 2004

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

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Abstract-Current statistics attribute up to 75% of the overall design costs of digital hardware and embedded system development to the verification task. In recent years, the trend to augment functional with formal verification tries to alleviate this problem. Efficient property checking algorithms allow automatic verification of middle-sized designs nowadays. However, the steadily increasing design sizes still leave verification the major bottleneck, because formal methodologies do not yet scale to very large designs.In this paper we present the formal verification tool SymC based on forward state space traversal and so-called ARautomata for property checking, both internally represented with BDDs. Furthermore, we introduce a new methodology called dynamic guiding. This methodology best suits multi-module concurrent Finite State Machine (FSM) designs. The aim of guiding is to reduce the intermediate and final BDD size, which in turn makes this verification technique applicable to larger designs. Our approach exploits abstract information of the design in the form of regular expressions and effectively guides the symbolic traversal depending on the verified property.

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“…We have implemented forward model checking by Iwashita [11,10] to see the correlation between forward model checking and using don't cares in model checking, because they are in common in that they try to avoid traversing unreachable states in fixpoint computation of model checking. Forward model checking is based on forward state traversal, while backward model checking is based on backward state traversal.…”

Section: Forward Vs Backward Model Checking With Ardcsmentioning

confidence: 99%

Approximate reachability don't cares for CTL model checking

Moon¹,

Jang²,

Hachtel³

et al. 1998

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '98

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RDCs (Reachability Don't Cares) can have a dramatic impact on the cost of CTL model checking [18]. Unfortunately, RDCs, being a global property, are often much more difficult to compute than the satisfying set of typical CTL formulas. We address this problem through the use of Approximate Reachability Don't Cares (ARDCs), computed with the algorithms developed for the VERITAS sequential synthesis package [4,5]. Approximate Reachable states represent an upper bound on the set of true reachable states, and thus a lower bound on the set of unreachable (Don't Care) states. ARDCs can be 10X to 100X (or much more for very large circuits) cheaper to compute than RDCs, and in some cases have the same dramatic effect on CTL model checking as the real RDCs. We also discuss the application of ARDCs to the problem of exact computation of the RDCs themselves. Experiments on industrial benchmarks show that order of magnitude speedups are possible, and occur frequently. The experimental results presented strongly support our claim that ARDCs play a safe and important way out of a serious dilemma: RDCs are necessary for tractable model checking of many large circuits, but the computation of the RDCs themselves is often intractable. We include, and theoretically justify, significant extensions of the VERITAS algorithms, and show that they can be up to an order of magnitude faster, while computing a virtually identical upper bound.

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Forward model checking techniques oriented to buggy designs

Cited by 29 publications

References 9 publications

A survey of recent advances in SAT-based formal verification

A survey of recent advances in SAT-based formal verification

Dynamic guiding of bounded property checking

Approximate reachability don't cares for CTL model checking

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