Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation 2008
DOI: 10.1145/1375581.1375591
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Foundations of the C++ concurrency memory model

Abstract: Currently multi-threaded C or C++ programs combine a singlethreaded programming language with a separate threads library. This is not entirely sound [7].We describe an effort, currently nearing completion, to address these issues by explicitly providing semantics for threads in the next revision of the C++ standard. Our approach is similar to that recently followed by Java [25], in that, at least for a welldefined and interesting subset of the language, we give sequentially consistent semantics to programs tha… Show more

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Cited by 351 publications
(124 citation statements)
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“…These are essentially causal-consistency models [4]. They allow independent readers to see independent writes (by different processors to different addresses) in different orders, as below (IRIW, see also [6]), but require that, in some sense, causality is respected: "P5. In a multiprocessor system, memory ordering obeys causality (memory ordering respects transitive visibility)".…”
Section: Iwp/amd64-314/x86-ccmentioning
confidence: 99%
“…These are essentially causal-consistency models [4]. They allow independent readers to see independent writes (by different processors to different addresses) in different orders, as below (IRIW, see also [6]), but require that, in some sense, causality is respected: "P5. In a multiprocessor system, memory ordering obeys causality (memory ordering respects transitive visibility)".…”
Section: Iwp/amd64-314/x86-ccmentioning
confidence: 99%
“…The C/C++11 Model The C/C++11 model [13,8,2,9] aims to support DRF-SC for simple programs (those using only locks and SC atomics), but also provides a range of low-level atomics that provide less synchronisation but without the cost of restoring full SC: release/acquire write/read pairs for message-passing synchronisation, relaxed atomics that should be implementable just with single machine-level loads and stores, and release/consume pairs to expose some dependency preservation guarantees of the hardware to make them available in the language. As we shall see, the semantics of all these remains problematic.…”
Section: Drf-sc or Catch Firementioning
confidence: 99%
“…There have been two previous results along these lines, but both were preliminary: Boehm and Adve [13] give a hand proof for a preliminary model that omits many features, while Batty et al [7,Thm. 5] give a hand proof based on an earlier version of their formal model that uses that model's notion of races for the SC semantics.…”
Section: Drf-sc or Catch Firementioning
confidence: 99%
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“…The emergence of mainstream multi-core processors as well as recent developments in language-level memory models [3,18], have stirred new interest in hardware-level memory models. The formal specification of memory models is challenging due to the many subtle differences between them.…”
Section: Introductionmentioning
confidence: 99%