Four innovative calibration algorithms for capacitive mismatch in 18‐bit redundant split SAR ADC

Abstract

Summary Four calibration algorithms based on the order statistics about capacitive mismatch are proposed for successive approximation register (SAR) analog‐to‐digital converter (ADC). An 18‐bit split capacitive SAR ADC architecture with redundant bits was used to verify the four calibration algorithms proposed. The main dynamic parameters of the SAR ADC were simulated in MATLAB by 500 Monte‐Carlo runs with a standard deviation of 0.1% (σ0/C0 = 0.001). And the simulation results of sorting and regrouping method II (SRGII) show that a 21.64‐dB enhancement of spurious‐free dynamic range (SFDR) and a 3.33‐bit improvement of effective number of bits (ENOB) have achieved respectively, whereas the simulation results of sorting and re‐exchanging method I (SREI) show that a 21.64‐dB enhancement of SFDR and a 3.34‐bit improvement of ENOB have achieved, respectively

Effective extraction method for triple errors in foreground calibration of TI‐ADCs

“…It is worth mentioning that the concept of calibration is not only limited to TI-ADCs as there are many other works about the correction of fundamental errors in the other architectures of ADCs. [3][4][5][6] Among the reported works of this criterion, the main emphasis was set on the correction of offset and gain mismatches since those errors do exist for other types of ADCs. On the other hand, timing skew mismatch particularly belongs to the TI-ADC structure.…”