Integration
 2023
DOI: 10.1016/j.vlsi.2022.12.012
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Four-input-C-element-based multiple-node-upset-self-recoverable latch designs

Shuo Cai
1
,
Caicai Xie
2
,
Yan Wen
3
et al.
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Cited by 5 publications
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Analysis and Design of a Low-Voltage Low-Power High SNDR Current-Mode Sample and Hold Circuit Based on CMOS Technology

Yu,
Gao,
Cai
et al. 2024
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Analysis and Design of a Low-Voltage Low-Power High SNDR Current-Mode Sample and Hold Circuit Based on CMOS Technology

Yu,
Gao,
Cai
et al. 2024
Wireless Pers Commun
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0
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A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements

Xu,
Tang,
Ma
et al. 2024
Microelectronics Journal
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A highly reliable and low-overhead quadruple-node-upset tolerant latch design

Xu,
Ai,
Ma
et al. 2024
Microelectronics Reliability
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