FP-SLIC: A Fully-Pipelined FPGA Implementation of Superpixel Image Segmentation

Ghaderi, Amir; Ahlberg, Carl; Ostgren, Magnus; Ekstrand, Fredrik; Ekström, Mikael

doi:10.1109/dsd57027.2022.00024

Cited by 4 publications

(2 citation statements)

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“…To address the issue of iterations, FP-SLIC [14] adopts a strategy of reducing the number of iterations. By limiting the iterations to just 2 times and implementing a fully pipelined FPGA architecture, the system's processing delay for an image with a resolution of 481x321 reaches 3.86 ms.…”

Section: Acceleration Of Slicmentioning

confidence: 99%

“…FMSLIC achieves a processing speed of 143 frames per second for input images. Despite these advancements in speed and memory efficiency, the iterative assignment and update steps make these approaches challenging to process images at 1000 FPS with a processing speed under 1 ms. FP-SLIC [14] directly reduces the number of iterations to a very small number, but it compromises the algorithm's robustness. To address this challenge, and as an extension of our previous work [15], this paper proposes a hardware-oriented SLIC algorithm with its system-level hardware implementation.…”

Section: Introductionmentioning

confidence: 99%

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Grid Sample Based Temporal Iteration for Fully Pipelined 1-ms SLIC Superpixel Segmentation System

LI,

HU,

FUCHIKAMI

et al. 2024

IEICE Trans. Inf. & Syst.

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A 1 millisecond (1-ms) vision system, which processes videos at 1000 frames per second (FPS) within 1 ms/frame delay, plays an increasingly important role in fields such as robotics and factory automation. Superpixel as one of the most extensively employed image oversegmentation methods is a crucial pre-processing step for reducing computations in various computer vision applications. Among the different superpixel methods, simple linear iterative clustering (SLIC) has gained widespread adoption due to its simplicity, effectiveness, and computational efficiency. However, the iterative assignment and update steps in SLIC make it challenging to achieve high processing speed. To address this limitation and develop a SLIC superpixel segmentation system with a 1 ms delay, this paper proposes grid sample based temporal iteration. By leveraging the high frame rate of the input video, the proposed method distributes the iterations into the temporal domain, ensuring that the system's delay keeps within one frame. Additionally, grid sample information is added as initialization information to the obtained superpixel centers for enhancing the stability of superpixels. Furthermore, a selective label propagation based pipeline architecture is proposed for parallel computation of all the possibilities of label propagation. This eliminates data dependency between adjacent pixels and enables a fully pipelined system. The evaluation results demonstrate that the proposed superpixel segmentation system achieves boundary recall and under-segmentation error comparable to the original SLIC algorithm. When considering label consistency, the proposed system surpasses the performance of state-of-the-art superpixel segmentation methods. Moreover, in terms of hardware performance, the proposed system processes 1000 FPS images with 0.985 ms/frame delay.

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Section: Acceleration Of Slicmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%