FPGA-accelerated Phase Rectification for a Stereo-based Phase Measuring Profilometry System

Junger, Christina; Heß, Albrecht; Rosenberger, Maik; Notni, Gunther

doi:10.1088/1742-6596/1065/3/032017

Cited by 5 publications

(4 citation statements)

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“…The extension of the compression algorithm in Ref. 8 is the additional subsample of the vertical and horizontal maps (see algorithm 1). Compared to the generated rectified images without and with compressed transformation maps, minor deviations of grey value are achieved (see subsection 4.2).…”

Section: Discussionmentioning

confidence: 99%

“…The following describes the reverse transformation of lens distortion and image correction (as used in FPGAs 4,7,8 ). The reverse transformation (see Figure 1) uses per camera two lens undistortion and image rectification transformation maps.…”

Section: Theoretical Backroundmentioning

confidence: 99%

“…In the first step, the pixel index in both UndistRectMaps are subtracted so the maps contain only the relative pixel offsets. 8 Then each UndistRectMap is subsampled. Subsampling is done according to a chequered pattern.…”

Section: Generation Of Compressed Rectification Mapsmentioning

confidence: 99%

“…Moreover, the offset deviations are calculated by the subtraction of the value from the value located two columns before. 8 The calculated offset deviations are stored with a sign bit in addition to the seven binary decimal bits. The values of the first two columns are rounded.…”

Section: Generation Of Compressed Rectification Mapsmentioning

confidence: 99%

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FPGA-based lens undistortion and image rectification for stereo vision applications

Junger

Heß

Rosenberger

et al. 2019

Photonics and Education in Measurement Science 2019

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Lens undistortion and image rectification is a commonly used pre-processing, e.g. for active or passive stereo vision to reduce the complexity of the search for matching points. The undistortion and rectification is implemented in a field programmable gate array (FPGA). The algorithm is performed pixel by pixel. The challenges of the implementation are the synchronisation of the data streams and the limited memory bandwidth. Due to the memory constraints, the algorithm utilises a pre-computed lossy compression of the rectification maps by a ratio of eight. The compressed maps occupy less space by ignoring the pixel indexes, sub-sampling both maps, and reducing repeated information in a row by forming differences to adjacent pixels. Undistorted and rectified images are calculated once without and once with the compressed transformation map. The deviation between the different computed images is minimal and negligible. The functionality of the hardware module, the decompression algorithm and the processing pipeline are described. The algorithm is validated on a Xilinx Zynq-7020 SoC. The stereo setup has a baseline with 46 mm and non-converged optical axis between the cameras. The cameras are configured at 1.3 Mpix @ 60 fps and distortion correction and rectification is performed in real time during image capture. With a camera resolution of 1280 pixels × 960 pixels and a maximum vertical shift of ± 20 pixels, the efficient hardware implementation utilizes 12 % of available block RAM resources.

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Section: Discussionmentioning

confidence: 99%

Section: Theoretical Backroundmentioning

confidence: 99%

Section: Generation Of Compressed Rectification Mapsmentioning

confidence: 99%

Section: Generation Of Compressed Rectification Mapsmentioning

confidence: 99%

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