FPGA-Accelerated Simulation of Computer Systems

Angepat, Hari; Chiou, Derek; Chung, Eric S.; Hoe, James C.

doi:10.2200/s00586ed1v01y201407cac029

Cited by 17 publications

(8 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…FPGA-based computer system emulators are common in industry and research. The following recent works are comparable with ours (see Table 3 for an overview and [57] for a broader survey of older approaches up to 2014): Open-Piton [44] is an open-source many-core research framework that can be implemented on an FPGA. It comes with a cachecoherent on-chip network and by now supports four different processor cores [18], [45], among them CVA6 also supported by HEROv2.…”

Section: Related Workmentioning

confidence: 59%

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

Kurth¹,

Forsberg²,

Benini³

2022

Preprint

View full text Add to dashboard Cite

Heterogeneous computers integrate general-purpose host processors with domain-specific accelerators to combine versatility with efficiency and high performance. To realize the full potential of heterogeneous computers, however, many hardware and software design challenges have to be overcome. While architectural and system simulators can be used to analyze heterogeneous computers, they are faced with unavoidable compromises between simulation speed and performance modeling accuracy. In this work we present HEROv2, an FPGA-based research platform that enables accurate and fast exploration of heterogeneous computers consisting of accelerators based on clusters of 32-bit RISC-V cores and an application-class 64-bit ARMv8 or RV64 host processor. HEROv2 allows to seamlessly share data between 64-bit hosts and 32-bit accelerators and comes with a fully open-source on-chip network, a unified heterogeneous programming interface, and a mixed-data-model, mixed-ISA heterogeneous compiler based on LLVM. We evaluate HEROv2 in four case studies from the application level over toolchain and system architecture down to accelerator microarchitecture. We demonstrate how HEROv2 enables effective research and development on the full stack of heterogeneous computing. For instance, the compiler can tile loops and infer data transfers to and from the accelerators, which leads to a speedup of up to 4.4× compared to the original program and in most cases is only 15 % slower than a handwritten implementation, which requires 2.6× more code.

show abstract

Section: Related Workmentioning

confidence: 59%

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

Kurth¹,

Forsberg²,

Benini³

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…In this section we discuss the approaches of softwarebased simulators such as Gem5, Sniper and ZSim along with FPGA assisted simulators for evaluation. An in-depth survey of FPGA accelerated simulation of computer systems is contained in [3].…”

Section: Related Workmentioning

confidence: 99%

“…FAST [9], [3] was one of the first systems to use FPGA accelerated timing models, implemented in Bluespec, that are driven by speculative functional execution of full-system simulation, using modified QEMU software [10]. QEMU determines the dynamic instruction trace passed to the timing models.…”

Section: Related Workmentioning

confidence: 99%

SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs

Iordanou

Palomar

Mawer

et al. 2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

View full text Add to dashboard Cite

This paper describes a flexible infrastructure for fast computer architecture simulation and prototyping of accelerator IP. A trend for System-on-Chips is to include application specific accelerators on the die. However, there is still a key research problem that needs to be addressed: How do hardware accelerators interact with the processors of a system and what is the impact on overall performance?To solve this problem, we propose an infrastructure that can directly simulate unmodified application executables with FPGA hardware accelerators. Unmodified application binaries are dynamically instrumented to generate processor load/store and program counter events and any memory accesses generated by accelerators, that are sent to an FPGA-based out-of-order pipeline model. The key features of our infrastructure are the ability to code exclusively at the user level, to dynamically discover and use available hardware models at run time, to test and simultaneously optimize hardware accelerators in an heterogeneous system.In terms of evaluation, we present a comparison between our system and Gem5 to demonstrate accuracy and relative performance, using the SPEC CPU benchmarks; even though our system is implemented on Zynq XC7045 which integrates dual 667MHz Arm Cortex-A9s with substantial FPGA resources, it outperforms Gem5 running on a Xeon E3 3.2 GHz with 32GBs of RAM. We also evaluate our infrastructure in simulating the interaction of accelerators with processors using accelerators taken from the Mach Benchmark Suite and other custom accelerators from computer vision applications.

show abstract

“…In this section we discuss the approaches of GEM5, Sniper, ZSim that are software based, and FAST and HAsim that utilise FPGA based, or assisted simulation systems for microarchitecture. An in-depth survey of FPGA accelerated simulation of computer systems is contained in [11].…”

Section: Related Workmentioning

confidence: 99%

The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation

Mawer

Palomar

Gorgovan³

et al. 2017

2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

View full text Add to dashboard Cite

In this paper we describe a flexible infrastructure that can directly interface unmodified application executables with FPGA hardware acceleration IP in order to 1), facilitate faster computer architecture simulation, and 2), to prototype microarchitecture or accelerator IP. Dynamic binary modification tool plugins are directly interfaced to the application under evaluation via flexible software interfaces provided by a userspace hardware control library that also manages access to a parameterised Bluespec IP library. We demonstrate the potential of our infrastructure with two use cases with unmodified application executables where, 1), an executable is dynamically instrumented to generate load/store and program counter events that are sent to FPGA hardware accelerated in-order microarchitecture pipeline, and memory hierarchy models, and 2), the design of a branch predictor is prototyped using an FPGA. The key features of our infrastructure are the ability to instrument at instruction level granularity, to code exclusively at the user level, and to dynamically discover and use available hardware models at run time, thus, we enable software developers to rapidly investigate and evaluate parameterised Bluespec microarchitecture and accelerator IP models. We present a comparison between our system and GEM5, the industry standard ARM architecture simulator, to demonstrate accuracy and relative performance; even though our system is implemented on an Xilinx Zynq 7000 FPGA board with tightly coupled FPGA and ARM Cortex A9 processors, it outperforms GEM5 running on a Xeon with 32GBs of RAM (400x vs 700x slowdown over native execution).

show abstract

FPGA-Accelerated Simulation of Computer Systems

Cited by 17 publications

References 34 publications

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs

The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation

Contact Info

Product

Resources

About