FPGA Acceleration for 3-D Low-Dose Tomographic Reconstruction

X-Ray Tomography Reconstruction Accelerated on FPGA Through High-Level Synthesis Tools

“…FPGA designs with HDL, as in [12], are known to provide efficient pipeline architecture, and this same efficiency can also be seen when using HLS tools. An asynchronous beam-based parallelism to accelerate the Mumford-Shah (MS) algorithm with a high data reuse rate and low external memory transactions has been proposed by Zhang et al [22]. Their approach reduces the computational cost of the backward projection to a lightweight operation.…”

“…The authors of [21] proposed a Ray-driven voxeltile parallel approach that maximizes the data reuse rate to take advantage of FPGA Block RAM (BRAM). In [22], they also proposed a parallel beam-based reconstruction on FPGA to exploit on-chip BRAM intensively. Both their works [21], [22] use Vivado HLS to synthesize the pipeline.…”

“…In [22], they also proposed a parallel beam-based reconstruction on FPGA to exploit on-chip BRAM intensively. Both their works [21], [22] use Vivado HLS to synthesize the pipeline. The authors of [23] proposed an FPGA design of iterative reconstruction for Transmission Electron Tomography (TET) by using data locality to optimize memory accesses.…”

OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration

“…Choi et al [17] proposed a Ray-driven voxel-tile parallel approach hence take advantage of FPGA BRAM blocks and the data reuse rate. Zhang et al [18] also proposed a parallel beambased reconstruction on FPGA to exploit on-chip BRAM intensively.…”