2015 IEEE International Conference on Bioinformatics and Biomedicine (BIBM) 2015
DOI: 10.1109/bibm.2015.7359892
|View full text |Cite
|
Sign up to set email alerts
|

FPGA acceleration of the pair-HMMs forward algorithm for DNA sequence analysis

Abstract: Many DNA sequence analysis tools have been developed to turn the massive raw DNA sequencing data generated by NGS (Next Generation Sequencing) platforms into biologically meaningful information. The pair-HMMs forward algorithm is widely used to calculate the overall alignment probability needed by a number of DNA analysis tools. In this paper, we propose a novel systolic array design to accelerate the pair-HMMs forward algorithm on FPGAs. A number of architectural features have been implemented to improve the … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
2
1

Citation Types

0
16
0

Year Published

2016
2016
2024
2024

Publication Types

Select...
4
2
2

Relationship

1
7

Authors

Journals

citations
Cited by 22 publications
(16 citation statements)
references
References 13 publications
0
16
0
Order By: Relevance
“…However, no source code is given. Other FPGA implementations were explored in [15], [16], [17], [18], [19], and [20]. GPU solutions include [21] and [22].…”
Section: B Hardware Accelerationmentioning
confidence: 99%
See 1 more Smart Citation
“…However, no source code is given. Other FPGA implementations were explored in [15], [16], [17], [18], [19], and [20]. GPU solutions include [21] and [22].…”
Section: B Hardware Accelerationmentioning
confidence: 99%
“…5) Compute Engine pipeline against parallel Processing Engines: Several other solutions [15], [17], [18], [20] use parallel arrays of PEs to compute partial diagonals of the matrix. While this solution may seem faster, this is not necessarily the case, and has some other drawbacks as well.…”
Section: A Hardware Accelerator Overviewmentioning
confidence: 99%
“…Research on increasing the speed of PFA by optimizations and acceleration can be found in In addition, [13] and [14] propose FPGA-based implementations of PFA on the Convey Computer platform and the IBM POWER8 platform, respectively. [13] employs a systolic array to map the algorithm on FPGAs.…”
Section: B Related Workmentioning
confidence: 99%
“…Research on increasing the speed of PFA by optimizations and acceleration can be found in In addition, [13] and [14] propose FPGA-based implementations of PFA on the Convey Computer platform and the IBM POWER8 platform, respectively. [13] employs a systolic array to map the algorithm on FPGAs. [14] proposes pipelined PEs (processing elements) of the systolic array, in addition to using the CAPI interface of the IBM POWER8 platform, which makes the data transfer more efficient.…”
Section: B Related Workmentioning
confidence: 99%
“…The Systolic Array (SA) is a parallel architecture that can be applied to a wide range of problems in a modular manner to simplify the design complexity. For the design of FPGA-based Pair-HMM forward algorithm accelerators, the one-dimensional SA [17,21,22] is a common approach and has some improved variants. The main structure of the SA is a pipeline, where the data flow among the Processing Elements (PEs).…”
Section: Introductionmentioning
confidence: 99%