DNNs (Deep Neural Networks) have solved various deep learning tasks, including classification problems, natural language processing, and speech recognition. However, this success comes with increased computational and memory requirements. Furthermore, recent deep learning research indicates that hardware implementations such as FPGAs (Field Programmable Gate Arrays) are preferable for implementing DNNs, and they fulfill the requirements due to the integrated circuits with programmable logic gates and connections. This technique offers hardware implementation flexibility, which makes it appealing for a wide range of applications, and that flexibility differs from the standard circuit. As a result, FPGAs are becoming increasingly popular as a hardware solution for accelerating systems and processes. This article presents a generic version of the design flow for automatically implementing DNN models on hardware by generating pipelined HDL codes, which can overcome the implementation problem. The article compares the design flow to other recent similar tools. The design flow is validated using a DNN to detect the diabetic patient from the Pima Indians dataset classification. This paper shows a high performance by reducing the latency by 4x the non-pipelined VHDL code and 1000x the software implementation using the TensorFlow framework without affecting the model's accuracy. Also, this design flow can serve in the early prediction of diabetes in the future-finally, a presentation of the conclusion and future works.