FPGA Architecture: Principles and Progression

Boutros, Andrew; Betz, Vaughn

doi:10.1109/mcas.2021.3071607

Cited by 95 publications

(22 citation statements)

References 79 publications

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“…A rather rough comparison between these two implementation approaches could be done as follows. According to [33], the fact that architectures built on FPGAs are, on average, 35 times larger and 4 times slower than those build on ASICs, these values can be converted to FPGA terms. However, the difference in the technology nodes (65 nm vs. 16 nm of the used FPGA) should be taken into account since there is a proportional increase in devices speed, according to the scaling factor.…”

Section: Board Implementation Results and Discussionmentioning

confidence: 99%

Novel Benes Network Routing Algorithm and Hardware Implementation

et al. 2022

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Benes/Clos networks constitute a particularly important part of interconnection networks and have been used in numerous areas, such as multi-processor systems, data centers and on-chip networks. They have also attracted great interest in the field of optical communications due to the increasing popularity of optical switches based on these architectures. There are numerous algorithms aimed at routing these types of networks, with varying degrees of utility. Linear algorithms, such as Sun Tsu and Opferman, were historically the first attempt to standardize the routing procedure of this types of networks. They require matrix-based calculations, which are very demanding in terms of resources and in some cases involve backtracking, which impairs their efficiency. Parallel solutions, such as Lee’s algorithm, were introduced later and provide a different answer that satisfy the requirements of high-performance networks. They are, however, extremely complex and demand even more resources. In both cases, hardware implementations reflect their algorithmic characteristics. In this paper, we attempt to design an algorithm that is simple enough to be implemented on a small field programmable gate array board while simultaneously efficient enough to be used in practical scenarios. The design itself is of a generic nature; therefore, its behavior across different sizes (8 × 8,16 × 16,32 × 32,64 × 64) is examined. The platform of implementation is a medium range FPGA specifically selected to represent the average hardware prototyping device. In the end, an overview of the algorithm’s imprint on the device is presented alongside other approaches, which include both hard and soft computing techniques.

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Section: Board Implementation Results and Discussionmentioning

confidence: 99%

Novel Benes Network Routing Algorithm and Hardware Implementation

et al. 2022

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“…In table 6 there is a comparison between our design and the author's work. 6 For the asic estimation values we used [8] [9]. Hardware is roughly 35 times smaller on ASIC and speed is 4 times faster.…”

Section: Section 4: Implementation and Simulationsmentioning

confidence: 99%

Implementation of high throughput system for data correction

Nikolaidis¹

2022

Preprint

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“…In general, the development of novel FPGA architectures and CAD algorithms depends mainly on a versatile framework that consists of three main components: (1) a set of benchmarks written in a hardware description language or synthesized using high-level synthesis, (2) an architecture model that captures the organization of FPGA blocks and routing architecture as well as area/timing/power models from circuit-level implementations, and (3) a CAD flow that synthesizes the given benchmarks then implements them on a given FPGA architecture [7]. Although most research efforts in the FPGA community are focused on architecture and CAD, benchmarks actually play a crucial role in this flow.…”

Section: Introductionmentioning

confidence: 99%

Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research

Arora¹,

Boutros²,

Rauch³

et al. 2021

Preprint

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With the prevalence of deep learning (DL) in many applications, researchers are investigating different ways of optimizing FPGA architecture and CAD to achieve better qualityof-results (QoR) on DL-based workloads. In this optimization process, benchmark circuits are an essential component; the QoR achieved on a set of benchmarks is the main driver for architecture and CAD design choices. However, current academic benchmark suites are inadequate, as they do not capture any designs from the DL domain. This work presents a new suite of DL acceleration benchmark circuits for FPGA architecture and CAD research, called Koios. This suite of 19 circuits covers a wide variety of accelerated neural networks, design sizes, implementation styles, abstraction levels, and numerical precisions. These designs are larger, more data parallel, more heterogeneous, more deeply pipelined, and utilize more FPGA architectural features compared to existing open-source benchmarks. This enables researchers to pin-point architectural inefficiencies for this class of workloads and optimize CAD tools on more realistic benchmarks that stress the CAD algorithms in different ways. In this paper, we describe the designs in our benchmark suite, present results of running them through the Verilog-to-Routing (VTR) flow using a recent FPGA architecture model, and identify key insights from the resulting metrics. On average, our benchmarks have 3.7× more netlist primitives, 1.8× and 4.7× higher DSP and BRAM densities, and 1.7× higher frequency with 1.9× more near-critical paths compared to the widely-used VTR suite. Finally, we present two example case studies showing how architectural exploration for DL-optimized FPGAs can be performed using our new benchmark suite.

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FPGA Architecture: Principles and Progression

Cited by 95 publications

References 79 publications

Novel Benes Network Routing Algorithm and Hardware Implementation

Novel Benes Network Routing Algorithm and Hardware Implementation

Implementation of high throughput system for data correction

Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research

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