FPGA architecture support for heterogeneous, relocatable partial bitstreams

Abstract

The use of partial dynamic reconfiguration in FPGA-based systems has grown in recent years as the spectrum of applications which use this feature has increased. For these systems, it is desirable to create a series of partial bitstreams which represent tasks which can be located in multiple regions in the FPGA fabric. While the transferal of homogeneous collections of lookup-table based logic blocks from region to region has been shown to be relatively straightforward, it is more difficult to transfer partial bitstreams which contain fixed-function resources, such as block RAMs and DSP blocks. In this paper we consider FPGA architecture enhancements which allow for the migration of partial bitstreams including fixed-function resources from region to region even if these resources are not located in the same position in each region. Our approach does not require significant, time-consuming place-and-route during the migration process. We quantify the cost of inserting additional routing resources into the FPGA architecture to allow for easy migration of heterogeneous, fixed-function resources. Our experiments show that this flexibility can be added for a relatively low overhead and performance penalty.

Partial Reconfiguration for Design Optimization

“…Applications of PR Today. Many academic projects have explored the potential of using PR (e.g., [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20]). Commercially, PR has been mainly used in a "role-and-shell" approach ([1], [21]).…”

FPGA Dynamic and Partial Reconfiguration

“…More recently researchers have proposed a new architecture for FPGAs with a single configuration plane that can support run-time relocation through PR [Huriaux et al 2014]. Due to their heterogeneous architecture, run-time circuit relocation is difficult in modern FPGAs as discussed in Section 2.2.…”