FPGA Based Accelerators for Financial Applications

Schryver, Christian De

doi:10.1007/978-3-319-15407-7

Cited by 15 publications

(1 citation statement)

References 19 publications

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“…In [10], a study is performed on HLS, for financial applications, which shows that the HLS hardware description languages are mature enough to be adopted from the industry. In [11], [12], several architectures are shown for acceleration of financial applications.…”

Section: Introductionmentioning

confidence: 99%

Hardware accelerators for financial applications in HDL and High Level Synthesis

Stamoulias

Kachris

Soudris

2017

2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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Many financial applications, like the one used for risk valuation, need high performance and low latency implementations to sustain the high volume of data that need to be processed. This paper presents a suite of high performance hardware accelerators for financial applications used in risk valuation (Black & Scholes, Black-76 and Binomial). The accelerators are developed in fixed point using HDL (VHDL) and in floating point using HLS languages. High Level Synthesis (HLS) allows fast implementation of hardware accelerators from the original legacy codes. The HLS hardware accelerators have been mapped onto a PCIe FPGA (ADM-KU3) board, through the Xilinx SDAccel framework and a thorough comparison in terms of resources, performance and accuracy has been performed. The performance evaluation shows that HLS can achieve higher accuracy due to the floating point, but requires up to 20% higher number of resources in terms of DSPs while the fixed-point implementations developed in HDL can save significant space in terms of resources but with limited accuracy compared to the software code.

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Section: Introductionmentioning

confidence: 99%