FPGA-based Control of STATCOM using a Compact SVPWM Algorithm

Abstract

This paper deals with the development and implementation of a space vector pulse width modulation (SVPWM) based Static Synchronous Compensator (STATCOM) controller using field programmable gate array (FPGA). Based on systemon-chip design technology, the entire real-time digital signal processing functions, including synchronous rotating frame transform, low-pass filter, three-phase phase-locked loop (PLL), dc voltage controller, and SVPWM generator, are all implemented and synthesized into a medium density FPGA chip. Experimental results obtained from a 500 kVA STATCOM are investigated to demonstrate high-performance of the design controller during steady-state and dynamic operation.