FPGA based Faster Implementation of MAC Unit in Residual Number System

Mohindroo, Bhavik; Paliwal, Atharv; Suneja, Kriti

doi:10.1109/incet49848.2020.9154105

Cited by 7 publications

(4 citation statements)

References 5 publications

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“…Hardware devices using RNS-based wavelet transform, which increase the performance of 3D image processing devices by up to 2.70 times, are described in [64]. FPGA accelerator for signal processing and machine learning algorithms implementation with multiply-accumulate units in RNS is developed in [65]. A convolutional neural network architecture with RNS-based digital filters hardware implementation is designed in [66].…”

Section:  mentioning

confidence: 99%

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

et al. 2022

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Medical imaging using different modalities has many problems. The main ones are low informativeness, various distortion noises, and a large amount of information. Fusion, denoising, and visual data compression are used to solve them in practice. Discrete wavelet transform is one way to implement various fusion, denoising, and compression methods for 2D and 3D medical image processing. Medical imaging systems produce increasingly accurate images with scanning technology and digital devices development. These images have improved quality using both higher spatial resolutions and color bit-depth. Processing a large volume of medical imaging data requires considerable resources and processing time. Modern wavelet-based devices for medical image processing do not meet the current performance demand. Hardware accelerators are being designed to solve this problem. This paper proposes new (fieldprogrammable gate array) FPGA accelerators using wavelet processing (WP) with scaled filter coefficients (SFC) and parallel computing in residue number system (RNS) to improve the performance of high-quality 3D medical image WP systems. The computational complexity is reduced using the developed WP method with SFC and the proposed wavelet filter coefficients scaling algorithm. Parallel computing is organized in RNS using moduli sets of a particular type. Hardware implementation of 3D medical image WP using the proposed FPGA accelerators increases device performance by 2.89-3.59 times, increasing the hardware resources by 1.18-3.29 times compared to state-of-the-art solutions. The device performance improvement is achieved while maintaining high-quality 3D medical image processing in peak signal-to-noise ratio terms.INDEX TERMS Medical image processing, discrete wavelet transform, scaled filter coefficients, residue number system, high-performance computing, hardware accelerator, field-programmable gate arrays.

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Section:  mentioning

confidence: 99%

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

et al. 2022

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“…The benefit of using these structures is that it allows savings in arithmetic resources in an FPGA. (Mohindroo, Paliwal and Suneja, 2020).…”

Section: Mac Unit Architecturementioning

confidence: 99%

“…Despite being cyclical, it can be carried out at a very high speed when implemented in an FPGA. (Mohindroo, Paliwal and Suneja, 2020).…”

Section: Journal Innovative Designmentioning

confidence: 99%

MAC-based Artificial Neural network for voice command recognition

Rodríguez-Ponce

2022

JID

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Artificial neural networks are one of the most popular families of machine learning algorithms of this decade. Although they exist since the middle of the last century, until recent years with the improvement of technology, they are being widely used in fields such as character, image, and voice recognition. There is a large number of works implementing neural networks for speech recognition; however, the approach has usually been for operation on a personal computer, which is not suitable for mobile applications. This article presents a neural network for voice command recognition, implemented in a compact FPGA card with low computational resources. In addition, it uses a multiplication and accumulation unit, called MAC, with which it achieves a smaller size and higher speed. This paper will be of interest to students or researchers working on machine learning mobile applications.

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“…Though these multipliers are fast, their computational complexity is very high. Therefore, in this paper, multiplications are avoided by adopting the Distributed Arithmetic (DA) approach to implement a radix-4 DIF-FFT [3]. DA is a mathematical technique used to calculate the sum of products.…”

Section: Introductionmentioning

confidence: 99%

International Journal of Electronics and Telecommunications

Jammu¹,

Muntha²,

Cheepurupalli³

et al. 2021

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Real-time data processing systems utilize Digital Signal Processing (DSP) functions as the base modules. Most of the DSP functions involve the implementation of Fast Fourier Transform (FFT) to convert the signals from one domain to another domain. The major bottleneck of Decimation in frequency-Fast Fourier Transform (DIF-FFT) implementation lies in using a number of Multipliers. Distributed arithmetic (DA) is considered as one of the efficient techniques to implement DIF-FFT. In this approach, the multipliers are not used. The proposed technique exploits the very advantage of the look-up table by storing the Twiddle factors, thereby avoiding the multipliers required in the butterfly structure. DIF-FFT using Distributed Arithmetic (DIF-FFT DA) models, with different adders such as Ripple carry adder (RCA), Carry-lookahead adder (CLA), and Sklansky prefix graph adder, are proposed in this paper. The three proposed models are synthesized using Cadence 6.1 EDA tools with a 45nm CMOS technology. Compared to the traditional method, it is observed that the area is improved by 53.11%, 53.35%, and 50.15%, power is improved by 42.31%, 42.52%, and 40.39%, and delay is improved by 45.26%, 45.42%, 41.80%, respectively.

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FPGA based Faster Implementation of MAC Unit in Residual Number System

Cited by 7 publications

References 5 publications

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

MAC-based Artificial Neural network for voice command recognition

International Journal of Electronics and Telecommunications

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