FPGA based floating-point library for CORDIC algorithms

Muñoz, Daniel M.; Sánchez, Diego F.; Llanos, Carlos H.; Ayala-Rincón, Maurício

doi:10.1109/spl.2010.5483002

Cited by 25 publications

(20 citation statements)

References 8 publications

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“…We use the average relative error(ARE) in different modes for accuracy analysis, the relative error is expressed by formula (5), where, results R is the hardware simulation results of our designed processor. We can see, in the condition of same ARE, the LUT and register consumption are less than that of the related design described in [15], [17] and [8]. Compared with references [16], the proposed design can achieve higher frequency.…”

Section: Synthesis Resultsmentioning

confidence: 72%

A Unified Reconfigurable CORDIC Processor for Floating-Point Arithmetic

Fang¹,

Li²,

Xie³

et al. 2018

Preprint

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This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximizes the sharing of common hardware circuit and achieves the area-delay-efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 1638416384 points target Synthetic Aperture Radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T FPGA platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.

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Section: Synthesis Resultsmentioning

confidence: 72%

A Unified Reconfigurable CORDIC Processor for Floating-Point Arithmetic

Fang¹,

Li²,

Xie³

et al. 2018

Preprint

View full text Add to dashboard Cite

show abstract

“…All operations are carried out using customized variable width floating-point arithmetic and trigonometric libraries based on the IEEE 754 standard. These units are described in [ 52 , 53 ] and provide much better precision and a larger dynamic range suited for small and large real numbers compared to fixed-point or simple integer arithmetic.…”

Section: Methodsmentioning

confidence: 99%

“…After that, the resulting value enters the activation function as described in Equation (4). The exponential operation uses a CORDIC module described in [ 53 ] while the rest of the arithmetic operators use the same floating-point units described in [ 52 ].…”

Section: Methodsmentioning

confidence: 99%

Sensor Fusion to Estimate the Depth and Width of the Weld Bead in Real Time in GMAW Processes

Bestard

Sampaio

Vargas

et al. 2018

Sensors

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The arc welding process is widely used in industry but its automatic control is limited by the difficulty in measuring the weld bead geometry and closing the control loop on the arc, which has adverse environmental conditions. To address this problem, this work proposes a system to capture the welding variables and send stimuli to the Gas Metal Arc Welding (GMAW) conventional process with a constant voltage power source, which allows weld bead geometry estimation with an open-loop control. Dynamic models of depth and width estimators of the weld bead are implemented based on the fusion of thermographic data, welding current and welding voltage in a multilayer perceptron neural network. The estimators were trained and validated off-line with data from a novel algorithm developed to extract the features of the infrared image, a laser profilometer was implemented to measure the bead dimensions and an image processing algorithm that measures depth by making a longitudinal cut in the weld bead. These estimators are optimized for embedded devices and real-time processing and were implemented on a Field-Programmable Gate Array (FPGA) device. Experiments to collect data, train and validate the estimators are presented and discussed. The results show that the proposed method is useful in industrial and research environments.

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“…Our previous results point out that the Taylor expansion approach has a lower execution time and a lower cost in logic area than the CORDIC-based solution. However, the CORDIC algorithm presents a better performance in terms of precision [26][27][28]. As will be explained below, this work focuses on solving the resource and timing constrains 6 International Journal of Reconfigurable Computing (see Section 4); therefore, the choice of using a Taylor expansion approach for computing the floating-point trigonometric operators can be justified.…”

Section: An Architectural Approach For Floating-point Operatorsmentioning

confidence: 99%

A Reconfigurable System Approach to the Direct Kinematics of a 5D.o.fRobotic Manipulator

Sánchez

Muñoz

Llanos

et al. 2010

International Journal of Reconfigurable Computing

Self Cite

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Hardware acceleration in high performance computer systems has a particular interest for many engineering and scientific applications in which a large number of arithmetic operations and transcendental functions must be computed. In this paper a hardware architecture for computing direct kinematics of robot manipulators with 5 degrees of freedom (5 D.o.f ) using floatingpoint arithmetic is presented for 32, 43, and 64 bit-width representations and it is implemented in Field Programmable Gate Arrays (FPGAs). The proposed architecture has been developed using several floating-point libraries for arithmetic and transcendental functions operators, allowing the designer to select (pre-synthesis) a suitable bit-width representation according to the accuracy and dynamic range, as well as the area, elapsed time and power consumption requirements of the application. Synthesis results demonstrate the effectiveness and high performance of the implemented cores on commercial FPGAs. Simulation results have been addressed in order to compute the Mean Square Error (MSE), using the Matlab as statistical estimator, validating the correct behavior of the implemented cores. Additionally, the processing time of the hardware architecture was compared with the same formulation implemented in software, using the PowerPC (FPGA embedded processor), demonstrating that the hardware architecture speeds-up by factor of 1298 the software implementation.

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FPGA based floating-point library for CORDIC algorithms

Cited by 25 publications

References 8 publications

A Unified Reconfigurable CORDIC Processor for Floating-Point Arithmetic

A Unified Reconfigurable CORDIC Processor for Floating-Point Arithmetic

Sensor Fusion to Estimate the Depth and Width of the Weld Bead in Real Time in GMAW Processes

A Reconfigurable System Approach to the Direct Kinematics of a 5D.o.fRobotic Manipulator

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