Fpga-Based Implementation of a Gaussian Smoothing Filter With Powers-of-Two Coefficients

Abstract

The purpose of the study is to develop methods for synthesizing a Gaussian filter that ensures simplified hardware and software implementation, particularly filters with powers-of-two coefficients. Such filters can provide effective denoising of images, including landscape maps, both natural and synthetically generated. The study also involves analyzing of methods for FPGA implementation, comparing their hardware complexity, performance, and noise reduction with traditional Gaussian filters. Results. An algorithm for rounding filter coefficients to powers of two, providing optimal approximation of the constructed filter to the original, is presented, along with examples of developed filters. Topics covered include FPGA implementation, based on the Xilinx Artix-7 FPGA. Filter structures, testing methods, simulation results, and verification of the scheme are discussed. Examples of the technological placement of the implemented scheme on the FPGA chip are provided. Comparative evaluations of FPGA resources and performance for proposed and traditional Gaussian filters are carried out. Digital modeling of the filters and noise reduction estimates for noisy images of the terrain surface are presented. The developed algorithm provides approximation of Gaussian filter coefficients as powers of two for a given window size and maximum number of bits with a relative error of no more than 0.18. Implementing the proposed filters on FPGA results in a hardware costs reduction with comparable performance. Computer simulation show that Gaussian filters both traditional and proposed effectively suppress additive white noise in images. Proposed filters improve the signal-to-noise ratio within 5-10 dB and practically match the filtering quality of traditional Gaussian filters.