FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

Abstract

This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum likelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types of carrier recovery loops and obtain a more robust performance in the procedure of carrier recovery. Besides, considering that, for MLFE, the accurate estimation of frequency offset is associated with the linear characteristic of its frequency discriminator (FD), the Coordinate Rotation Digital Computer (CORDIC) algorithm is introduced into the FD based on MLFE to unwrap linearly phase difference. The frequency offset contained within the phase difference unwrapped is estimated by the MLFE implemented just using some shifter and multiplyaccumulate units to assist the ADCOL to lock quickly and precisely. The joint simulation results of ModelSim and MATLAB show that the performances of the proposed ADCRL in locked-in time and range are superior to those of the ADCOL. On the other hand, a systematic design procedure based on FPGA for the proposed ADCRL is also presented.

Software Defined Radio Implementation of a QPSK Modulator/Demodulator in an Extensive Hardware Platform Based on FPGAs Xilinx ZYNQ

“…Whereas scalability which is related to modularity, allows in a general scope, the system to be increased with an outlook on capacity expansions, such as added channels in a base station. While the system's efficiency links to three features which can be quantized through energy consumption, system cost and computational magnitude (Lathi and Ding, 2009;Kostic, 1994;Wang et al, 2014).…”

Digital receiver for addressed direction finding of modern communication standards

“…• it takes one decision on the packet frequency offset without continues monitoring [4]. It increases the stability of the circuit; • It does not require a data rate multiple of the symbol rate, at the same time it provides a rough frequency tuning with accuracy about 20 kHz, which is sufficient to receive the symbols with DQPSK, CCK modulation type [7].…”