2018 10th Computer Science and Electronic Engineering (CEEC) 2018
DOI: 10.1109/ceec.2018.8674196
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FPGA based Implementation of ECDSA for Secured ITS

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Cited by 3 publications
(2 citation statements)
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“…It is important to remember that a cryptographic signature generated with an ECDSA algorithm having the size 64 bits has the same security level as an Rivest Shamir Adleman (RSA) cryptographic signature of size 2048 bits. In recent years, research on ECDSA hardware implementation has become very popular [1][2][3][4][5][6]. A lot of research is being done to improve ECDSA's performance and this has led to a large number of implementations.…”
Section: Introductionmentioning
confidence: 99%
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“…It is important to remember that a cryptographic signature generated with an ECDSA algorithm having the size 64 bits has the same security level as an Rivest Shamir Adleman (RSA) cryptographic signature of size 2048 bits. In recent years, research on ECDSA hardware implementation has become very popular [1][2][3][4][5][6]. A lot of research is being done to improve ECDSA's performance and this has led to a large number of implementations.…”
Section: Introductionmentioning
confidence: 99%
“…A lot of research is being done to improve ECDSA's performance and this has led to a large number of implementations. In 2018, Asif et al [6] developed a new architectural design of the ECDSA algorithm, for intelligent transport system (ITS) applications, which is able to validate the constraints in real time. The authors employed parallel processing techniques to minimize hardware delays which reduces real-time security and end-to-end delay of ITS messages.…”
Section: Introductionmentioning
confidence: 99%