FPGA-Based Implementation of Ship Detection for Satellite On-Board Processing

Xu, Ming; Chen, Liang; Shi, Hao; Yang, Zhu; Jiahao, Li; Long, Teng

doi:10.1109/jstars.2022.3218440

Cited by 10 publications

(7 citation statements)

References 37 publications

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“…It improves the pertinence and timeliness of user information acquisition, multiplies the application efficiency of satellites, and supports the demand for intelligent observation missions in the future [5]. However, in the overall operating environment of the satellite platform, not only the algorithm accuracy and operating speed need to be considered, but also the limited power budget and system reliability [6].…”

Section: Introductionmentioning

confidence: 99%

Hardware-Optimized Architecture of On-Board Registration for Remote-Sensing Images —Take SURF as an Example

Du,

Yang,

Zhong

et al. 2024

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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On-board processing has become an inevitable choice for the development of remote sensing satellites. For the satellites with dual-line array asynchronous push-broom mode, image registration is crucial for pixel localization and alignment between dual-band strip data. However, due to the high computational complexity of feature detection and feature extraction, it is still a challenge to realize real-time registration for on-board edge devices with limited computing power and power consumption. Therefore, this paper proposes a hardwareoptimized architecture with high-performance and low-energy for on-board registration based on "ARM+FPGA". On one hand, optimized methods for the image registration algorithm are proposed from both software and hardware perspectives, providing a solution for on-board registration. On the other hand, in the face of the current interface environment of satellites, a design scheme for versatile hardware architecture is proposed. It provides a foundational technical route for hardware deployment of on-board processing. Experimental results show that in this hardware-accelerated architecture, the average acceleration effect of registration algorithm can reach 15 times compared to the unoptimized version. Additionally, the average power consumption is reduced by 60%, and the hardware resource utilization is less than 40%. Importantly, the algorithm's accuracy remains unaffected by these optimizations. The onboard intelligent processing payload deployed with this hardware architecture has been successfully launched and validated in February 2022 in the orbit of the MN200Sar-1 satellite from China. It improves the real-time capability for on-board processing, and aims to achieve a new imaging mechanism where target and information transmission replace strip image transmission. Index Terms-Field Programmable Gate Array (FPGA), Hardware acceleration, On-board processing, Speed-up Robust Features (SURF), High-Level Synthesis (HLS).

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Section: Introductionmentioning

confidence: 99%

Hardware-Optimized Architecture of On-Board Registration for Remote-Sensing Images —Take SURF as an Example

Du,

Yang,

Zhong

et al. 2024

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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“…The artificial neural network (ANN) model implemented on FPGA can also be used to extract the features from an input image and to encrypt the same image using asymmetric encryption algorithms [40]. Nowadays onboard processing using FPGA model is used in many remote sensing missions such as automatic target detection [41] and ship detection [42]. In onboard processing, the images are induced with some errors due to single-induced upsets.…”

Section: Introductionmentioning

confidence: 99%

Comparative study on satellite based image encryption methods: a survey

Vasudevaiah,

Shivaswamy

2024

IJECE

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The availability of high-resolution satellite images increases with advancements in remote sensing technology. These satellite images are used in various earth observation applications such as disaster management, military applications, weather forecasting, land use and cover, and many more. Satellite images have large volumes stored in memory devices. These satellite images are transmitted to the ground station for processing and analysis. In these cases, images are vulnerable to privacy issues. As technology advances, onboard processing of satellite images using intelligent systems processes the images faster. A model such as field programmable gate arrays (FPGA) is used in onboard processing to process satellite images. However, images are susceptible to faults induced by harsh radiation environments in space. Encryption is one of the most assured methods to provide privacy to satellite images. Hence, encryption of satellite images during processing, storage, and transmission is the present rising demand. There are various encryption methods implemented using algorithms such as advanced encryption standard (AES), homomorphic, advanced encryption standard-counter (AES-CTR), and chaotic maps. Concurrent processing and encryption of images using MapReduce with Hadoop Framework perform the task faster. The focus of this paper is a comparative study of the various encryption methods used in recent years.

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“…Of course, these sort of devices are not suitable for embedded processing, in particular for avionics, where there are very strong design constraints on power consumption. This is a major problem to address, since hyperspectral sensors are very often mounted on board planes and satellites [9]- [12]. Recently, more specific devices such as TPUs and VPUs [13] that feature low power consumption have surfaced to bridge the gap between power and performance; however they are coprocessors and are unable to operate standalone, still requiring a CPU.…”

Section: Introductionmentioning

confidence: 99%

Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA

Morcillo,

Báscones,

González

et al. 2024

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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k-means stands out as one of the most common clustering algorithms, widely employed for classification in hyperspectral imaging. In this context, large amounts of data are gathered by sensors that are embedded into satellites with strict constraints in terms of power consumption, weight, physical space or radiation tolerance. Since communication bandwidth is also limited, data processing must be performed on board. However, meeting all those constraints also entails a significant trade-off with computing performance. The aim of this work is clustering hyperspectral images in real-time. Custom hardware has been designed with the objective of reducing overhead and maximizing performance, by exploiting several acceleration techniques. The implementation targets a space-grade Xilinx Kintex FPGA, that features low power consumption and is shielded against radiation. The design has a deep pipelined architecture, able to process all bands of each hyperspectral pixel in parallel. In consequence, it attains a throughput of 100M hyperspectral pixels per second, even with a discrete use of FPGA resources. In addition, it is also fully parametric, with on-the-fly adaptation to different kinds of images and clustering configurations.Compared to previous implementations, ours takes advantage of a fully RTL design that avoids CPU bottlenecks and HLS design overheads. It also has a fixed throughput regardless of image or clustering properties, while having lower FPGA resource usage than performance-wise equivalent implementations.

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FPGA-Based Implementation of Ship Detection for Satellite On-Board Processing

Cited by 10 publications

References 37 publications

Hardware-Optimized Architecture of On-Board Registration for Remote-Sensing Images —Take SURF as an Example

Hardware-Optimized Architecture of On-Board Registration for Remote-Sensing Images —Take SURF as an Example

Comparative study on satellite based image encryption methods: a survey

Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA

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