FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling

Shimoda, Masayuki; Sada, Youki; Nakahara, Hiroki

doi:10.1007/s11265-021-01642-6

Cited by 6 publications

(5 citation statements)

References 39 publications

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“…Image classification, object detection, and semantic segmentation are just few of the computer vision applications where convolutional neural networks (CNNs) [8,9] have shown amazing performance. Convolutional layers, pooling layers, and fully linked layers are the standard building blocks of a normal CNN [10].…”

Section: Cnns and Fpga-based Pipeliningmentioning

confidence: 99%

Convolutional Neural Networks using FPGA-based Pipelining

Ali¹,

Ali

2023

ijcsm

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In order to speed up convolutional neural networks (CNNs), this study gives a complete overview of the use of FPGA-based pipelining for hardware acceleration of CNNs. These days, most people use convolutional neural networks (CNNs) to perform computer vision tasks like picture categorization and object recognition. The processing and memory demands of CNNs, however, can be excessive, especially for real-time applications. In order to speed up CNNs, FPGA-based pipelining has emerged as a viable option thanks to its parallel processing capabilities and low power consumption. The examination describes the fundamentals of FPGA-based pipelining and the basic structure of convolutional neural networks (CNNs). The current best practises for developing pipelined accelerators for CNNs on FPGAs are then reviewed, covering topics like partitioning and pipelining. Area and power limits, memory needs, and latency considerations are only some of the difficulties and trade-offs discussed in the article. In addition, the survey evaluates and contrasts the various pipelined FPGA accelerators for CNNs in terms of performance, energy consumption, and resource utilisation. Future directions and potential research areas are also discussed in the paper, such as the use of approximate computing techniques, the integration of reconfigurable architectures with emerging memory technologies, and the exploration of hybrid architectures that combine FPGAs and other hardware accelerators. This survey was created to aid researchers and practitioners in developing efficient and effective hardware accelerators for neural networks by providing a thorough overview of current trends and issues in FPGA-based pipelining for CNNs.

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Section: Cnns and Fpga-based Pipeliningmentioning

confidence: 99%

Convolutional Neural Networks using FPGA-based Pipelining

Ali¹,

Ali

2023

ijcsm

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“…In [64], [262], deconvolution is replaced by bi-linear interpolation. The authors use a tiled approach, so they divide the input image into smaller images and perform the segmentation on them.…”

Section: Semantic Segmentationmentioning

confidence: 99%

“…FCN differs from CNN in the last layer, where the fully connected layer is replaced by a convolutional layer. Some techniques used in [64], [262] are also applied, including filter-wise pruning, bi-linear interpolation, coordinate memory overhead. In this case, the evaluation is on Camvid dataset.…”

Section: Semantic Segmentationmentioning

confidence: 99%

A Survey of FPGA-Based Vision Systems for Autonomous Cars

et al. 2022

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On the road to making self-driving cars a reality, academic and industrial researchers are working hard to continue to increase safety while meeting technical and regulatory constraints Understanding the surrounding environment is a fundamental task in self-driving cars. It requires combining complex computer vision algorithms. Although state-of-the-art algorithms achieve good accuracy, their implementations often require powerful computing platforms with high power consumption. In some cases, the processing speed does not meet real-time constraints. FPGA platforms are often used to implement a category of latency-critical algorithms that demand maximum performance and energy efficiency. Since self-driving car computer vision functions fall into this category, one could expect to see a wide adoption of FPGAs in autonomous cars. In this paper, we survey the computer vision FPGA-based works from the literature targeting automotive applications over the last decade. Based on the survey, we identify the strengths and weaknesses of FPGAs in this domain and future research opportunities and challenges.INDEX TERMS autonomous car, feature extraction, field programmable gate arrays, image classification, object detection, reconfigurable architectures Self-driving functions can be implemented in several computing platforms such as ASICs, CPUs, DSPs, GPUs, FPGAs, or in heterogeneous platforms composed by any

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“…All models can reach the same or similar MAE of their non-pruned full model counterparts. This suggests that our proposed pruning technique is a viable approach to reduce the model parameters under hardware resource constraints or to decrease hardware processing cycles [11,12].…”

Section: Neural Network Model Pruningmentioning

confidence: 99%

Waveform processing using neural network algorithms on the front-end electronics

Miryala¹,

Mittal²,

Ren³

et al. 2022

J. Inst.

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In a multi-channel radiation detector readout system, waveform sampling, digitization, and raw data transmission to the data acquisition system constitute a conventional processing chain. The deposited energy on the sensor is estimated by extracting peak amplitudes, area under pulse envelopes from the raw data, and starting times of signals or time of arrivals. However, such quantities can be estimated using machine learning algorithms on the front-end Application-Specific Integrated Circuits (ASICs), often termed as “edge computing”. Edge computation offers enormous benefits, especially when the analytical forms are not fully known or the registered waveform suffers from noise and imperfections of practical implementations. In this work, we aim to predict peak amplitude from a single waveform snippet whose rising and falling edges containing only 3 to 4 samples. We thoroughly studied two well-accepted neural network algorithms, Multi-Layer Perceptron (MLP) and Convolutional Neural Network (CNN) by varying their model sizes. To better fit front-end electronics, neural network model reduction techniques, such as network pruning methods and variable-bit quantization approaches, were also studied. By combining pruning and quantization, our best performing model has the size of 1.5 KB, reduced from 16.6 KB of its full model counterpart. It can reach mean absolute error of 0.034 comparing to that of a naive baseline of 0.135. Such parameter-efficient and predictive neural network models established feasibility and practicality of their deployment on front-end ASICs.

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FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling

Cited by 6 publications

References 39 publications

Convolutional Neural Networks using FPGA-based Pipelining

Convolutional Neural Networks using FPGA-based Pipelining

A Survey of FPGA-Based Vision Systems for Autonomous Cars

Waveform processing using neural network algorithms on the front-end electronics

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