2020 IEEE 31st International Conference on Application-Specific Systems, Architectures and Processors (ASAP) 2020
DOI: 10.1109/asap49362.2020.00014
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FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing

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“…Figure 2 shows a block diagram of our system. The FPGA accelerator contains a packet receiver, packetheader analyzer, NTC, statistics aggregator, and microburst detector [11,12]. The packet receiver supports 10-Gigabit Ethernet.…”
Section: System Architecturementioning
confidence: 99%
“…Figure 2 shows a block diagram of our system. The FPGA accelerator contains a packet receiver, packetheader analyzer, NTC, statistics aggregator, and microburst detector [11,12]. The packet receiver supports 10-Gigabit Ethernet.…”
Section: System Architecturementioning
confidence: 99%