FPGA Based Novel High Speed DAQ System Design with Error Correction

Mandal, Swagata; Sau, Suman; Chakrabarti, Amlan; Saini, Jogendra; Pal, Sushanta Kumar; Chattopadhyay, S.

doi:10.1109/isvlsi.2015.80

Cited by 2 publications

(1 citation statement)

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“…This solution uses the cipher’s linear operations, involving XOR and shift to detect errors in the merged transformations [ 31 ]. A data acquisition system is proposed by Mandal et al in [ 32 ] which supports high-speed data communication and reaches multi-bit error correction. An error correction procedure for the Advanced Encryption Standard (AES) is proposed by Biernat et al in [ 33 ]: a prediction for each AES transformation is implemented, detecting all bit errors of odd order and most bit errors of even order injected into a single bit of the data block.…”

Section: Related Workmentioning

confidence: 99%

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Algredo‐Badillo

Ramírez-Gutiérrez

Morales-Rosales

et al. 2021

Sensors

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Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.

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Section: Related Workmentioning

confidence: 99%