FPGA Based Optimized Reconfigurable Base-2 Constant Coefficient Multiplier Architecture for Image Filtering

Abstract

Image convolution using FPGA has been comprehensively used for noise removal of Reconfigurable computing based image Processing Algorithm. Particularly these filters are widely used in embedded computer vision applications like edge detection and Feature extraction analysis. Practical implementation of filter requires enormous computational requirement. The multiplier plays very important role in the image convolution. The existed multiplier design requires more computational complexity for the 3x3 test image. For this the proposed reconfigurable constant coefficient multiplier uses base-2 Common sub expression algorithm. which reduces the computational complexity in a better way. The proposed 2D-convolution in image application is the value of resultant output is multiplication of image pixel with corresponding kernel value. In this work the realization of 2D convolution to be done using proposed constant coefficient multiplier and analyzed using Xilinx Virtex-5 FPGA platform