FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification

Qasaimeh, Murad; Sagahyroon, Assim; Shanableh, Tamer

doi:10.1109/tci.2015.2424077

Cited by 47 publications

(25 citation statements)

References 16 publications

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“…Interestingly, a hardware/software co-design method of SVM classification of melanoma images is to be considered as an added work in literature that was realized on the recent hybrid Zynq platform using the HLS design methodology. In addition, our proposed implementation achieved lower hardware resources utilization than some of the previous FPGA-based SVM classification implementations of different applications in literature [10], [12], [21], [23], [25], [34], [36]. Concerning power consumption, our implementation demonstrated lower power dissipation than other related work [6], [12], [25].…”

Section: Resultsmentioning

confidence: 80%

“…However, there is a trade-off between classification accuracy and high performance, and meeting embedded systems constraints of low level of area and power consumption. Due to some simplifications performed for the hardware implementation, some loss in accuracy rating occurs [12,13], [17], [26,27]. Moreover, most designs in existing literature were implemented on old versions of FPGAs and only a very limited number used recent ones [9], [28].…”

Section: Introductionmentioning

confidence: 99%

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Hardware Acceleration of SVM-Based Classifier for Melanoma Images

Afifi

GholamHosseini

Sinha

2016

Image and Video Technology – PSIVT 2015 Workshops

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Abstract. Melanoma is the most aggressive form of skin cancer which is responsible for the majority of skin cancer related deaths. Recently, image-based Computer Aided Diagnosis (CAD) systems are being increasingly used to help skin cancer specialists in detecting melanoma lesions early, and consequently reduce mortality rates. In this paper, we implement the most compute-intensive classification stage in the CAD onto FPGA, aiming to achieve acceleration of the system for deploying as an embedded device. A hardware/software co-design approach was proposed for implementing the Support Vector Machine (SVM) classifier for classifying melanoma images online in real-time. The hybrid Zynq platform was used for implementing the proposed architecture of the SVM classifier designed using the High Level Synthesis design methodology. The implemented SVM classification system on Zynq demonstrated high performance with low resources utilization and power consumption, meeting several embedded systems constraints.

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Section: Resultsmentioning

confidence: 80%

Section: Introductionmentioning

confidence: 99%

Hardware Acceleration of SVM-Based Classifier for Melanoma Images

Afifi

GholamHosseini

Sinha

2016

Image and Video Technology – PSIVT 2015 Workshops

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“…Due to the numerous advantages, image stitching is widely used for self-driving cars/drones, 3D mapping, defense systems, and medical imaging [2] - [4]. However, due to the intense computing most of the image stitching hardware has been implemented with extremely high cost servers or high performance, multi-GPU/DSP platforms which require enormous computing and power usage [5] - [8].…”

Section: Introductionmentioning

confidence: 99%

Virtual Prototyping of Area-Based Fast Image Stitching Algorithm

Mudragada¹,

Lee²,

Kim³

2019

J Multimed Inf Syst

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This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two 1280 × 1024 sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

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“…Two hardware/software co‐designs using embedded FPGA processors are presented in Bonato et al and Yao et al These implementations are able to generate descriptors for quarter video graphics array (VGA) and VGA images at 30 frames per second (fps). In Qasaimeh et al, an all‐hardware FPGA implementations for VGA images, achieving 30 fps, is described. On the other hand, in Huang et al and Chiu et al, two complementary metal oxide semiconductor implementations are proposed.…”

Section: Introductionmentioning

confidence: 99%

An all‐hardware implementation of the subpixel refinement stage in SIFT algorithm

Rubio‐Ibáñez

Ruiz‐Merino

Doménech‐Asensi

et al. 2018

Circuit Theory & Apps

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This paper proposes an all-hardware architecture to perform the subpixel refinement operation in the scale invariant transform algorithm. Although the literature describes several hardware implementations of this algorithm, due to its complexity, most of them are based on simplifications of it. These implementations normally exclude the subpixel refinement stage, which, however, is an essential process to obtain accurate results in image matching applications.The architecture has been described in very high-speed integrated circuit hardware description language at register transfer level and synthesized on a Xilinx Zynq 7020 device. The latency of the proposed architecture to generate a refinement operation is 211 clock cycles, and the throughput achieved exploiting pipeline techniques is 64 cycles. The architecture uses fixed-point data representation and has been tested with images from known databases, yielding very good performance compared with the floating-point software implementation of the algorithm.

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FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification

Cited by 47 publications

References 16 publications

Hardware Acceleration of SVM-Based Classifier for Melanoma Images

Hardware Acceleration of SVM-Based Classifier for Melanoma Images

Virtual Prototyping of Area-Based Fast Image Stitching Algorithm

An all‐hardware implementation of the subpixel refinement stage in SIFT algorithm

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