FPGA-based Real-time Abnormal Packet Detector for Critical Industrial Network

Kang, Ji‐Hwan; Kim, Taein; Park, Jaehyun

doi:10.1109/iscc47284.2019.8969630

Cited by 7 publications

(2 citation statements)

References 14 publications

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“…Recursive Flow Classification (RFC) is a heuristic algorithm, which is used for live packet classification on the proposed framework. The RFC algorithm (17) classifies packets by mapping the packet header bits 'S' to a bit action identifier 'T, ' wherein T = log N, T<<S. RFC constantly calculates the action for every one of the 2 S dissimilar data packet headers. RFC tries to do any such mapping multiple times in order to get the best result.…”

Section: Methodsmentioning

confidence: 99%

Proactive Analysis and Detection of Cyber-attacks using Deep Learning Techniques

Abirami,

Lakshmanaprakash,

Priya

et al. 2024

IJST

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Objectives: This study objective is to create a proactive forensic framework with a classification model to identify the malicious content to avoid cyber-attacks. Methods: In this proposed work, a novel framework is introduced to analyze and detect network attacks before it happens. It monitors the network packet flow, captures the packets, analyzes the packet flow proactively, and detects cyber-attacks using different machine learning algorithms and Deep Convolution Neural network (CNN) technique. The KDD dataset is used in this experiment with 30% for testing and 80% for training. Findings: The simulation results show that the detection percentage of the proposed framework reaches a maximum of 95.92% in different scenarios. It is approximately 10% higher than the existing proactive frameworks for example Gawand’s model, Ahmetoglu’s model and many more. Novelty and applications: The proposed framework is a proactive model which detects the cyber-attack in prior to avoid cyber-attacks. The deep CNN model highly efficient for detecting cyber-attack. Keywords: Proactive Forensic Framework, Deep CNN, Classification Algorithms, Cyber attack detection, Intrusion Detection System

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Section: Methodsmentioning

confidence: 99%

Proactive Analysis and Detection of Cyber-attacks using Deep Learning Techniques

Abirami,

Lakshmanaprakash,

Priya

et al. 2024

IJST

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“…In existing work we see robust FPGAs used in large scale server-side applications to supplement network security. FPGA's speed makes them useful for real-time network intrusion detection and device identification in closed critical industrial networks [14]. For example, a proposed k-means k-modes clustering architecture in [15] implements highly configurable input parameters with interconnected blocks to reduce the need for reconfiguration.…”

Section: Hls Simulationmentioning

confidence: 99%

An Efficient SDN Architecture for Smart Home Security Accelerated by FPGA

Gordon¹,

Park²,

Tushir³

et al. 2021

Preprint

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With the rise in Internet of Things (IoT) devices, home network management and security are becoming complex.There is an urgent requirement to make smart home network management efficient. This work proposes an SDN-based architecture to secure smart home networks through K-Nearest Neighbor (KNN) based device classifications and malicious traffic detection. The efficiency is further enhanced by offloading the computation-intensive KNN model to Field Programmable Gate Arrays (FPGA), which offers parallel processing power of GPU platforms at lower costs and higher efficiencies, and can be used to accelerate time-sensitive tasks. The proposed parallelization and implementation of KNN on FPGA are achieved by using the Vivado Design Suite from Xilinx and High-Level Synthesis (HLS). When optimized with 10-fold cross-validation, the proposed solution for KNN consistently exhibits the best performances on FPGA when compared with four alternative KNN instances (i.e., 78% faster than the parallel Bubble Sortbased implementation and 99% faster than the other three sorting algorithms). Moreover, with 36,225 training samples, the proposed KNN solution classifies a test query with 95% accuracy in approximately 4 milliseconds on FPGA compared to 57 seconds on a CPU platform.

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