FPGA-Based Real-Time Pedestrian Detection on High-Resolution Images

Hähnle, M.; Saxen, Frerk; Hisung, Matthias; Brunsmann, U.; Doll, Konrad

doi:10.1109/cvprw.2013.95

Cited by 97 publications

(69 citation statements)

References 11 publications

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“…This is done using (9) and if the result is positive it is a pedestrian class else a non-pedestrian class. …”

Section: International Journal For Research In Applied Science and Engimentioning

confidence: 99%

FPGA Accelerated Pedestrian Detection System

Kalshaonkar¹

2017

IJRASET

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This paper focuses on developing a Pedestrian Detection System that is accelerated using a Zedboard. A part of the design is implemented on FPGA and the remaining is implemented in Matlab R2015a. Histogram of Oriented Gradients (HOG) has been used for detection purpose and Linear Support Vector Machine (LSVM) has been used for classification. This system gave an accuracy of 93.27%, a True Positive Rate of 92.27% and a False Positive Rate of 4%. Also the system was faster than the software implementation.

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“…This is done using (9) and if the result is positive it is a pedestrian class else a non-pedestrian class. …”

Section: International Journal For Research In Applied Science and Engimentioning

confidence: 99%

FPGA Accelerated Pedestrian Detection System

Kalshaonkar¹

2017

IJRASET

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“…In none of the papers above was the reduced bit-width used for HOG detection. A pedestrian detection system processing 18 scales of 1920 × 1080 resolution images at 64 fps was reported in [20]. Its throughput was estimated via simulation.…”

Section: Background a Related Workmentioning

confidence: 99%

Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs

Najjar

Roy-Chowdhury

2015

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-The reliance on object or people detection is rapidly growing beyond surveillance to industrial and social applications. The Histogram of Oriented Gradients (HOG), one of the most popular object detection algorithms, achieves high detection accuracy but delivers just under one frame-per-second (fps) on a high-end CPU. FPGA accelerations of this algorithm are limited by the intensive floating-point computations. All current fixedpoint HOG implementations use large bit-width to maintain detection accuracy, or perform poorly at reduced data precision. In this paper we introduce the full-image evaluation methodology to explore the FPGA implementation of HOG using reduced bit-width. This approach lessens the required area resources on the FPGA and increases the clock frequency and hence the throughput per device through increased parallelism. We evaluate the detection accuracy of the fixed-point HOG by applying state-of-the-art computer vision pedestrian detection evaluation metrics and show it performs as well as the original floatingpoint code from OpenCV. We then show our single FPGA implementation achieves a 68.7x higher throughput than a highend CPU, 5.1x higher than a high-end GPU, and 7.8x higher than the same implementation using floating-point on the same FPGA. A power consumption comparison for different platforms shows our fixed-point FPGA implementation uses 130x less power than CPU, and 31x less energy than GPU to process one image.

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“…An ASIC version of this design is presented in [9] with dual cores to enable voltage scaling down to 0.7 V with power consumption of 40.3mW for 1080HD at 30 fps. In [5], the detector is implemented on an FPGA and can process 1080HD at 64 fps multi-scale support by time-multiplexing 18 scales across 3 successive frames. It should be noted that these implementations have relatively large on-chip memory requirements (e.g., [9] Fig.…”

Section: Previous Workmentioning

confidence: 99%

Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support

Suleiman

Sze

2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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Abstract-In this paper, we present a real-time and energyefficient multi-scale object detector using Histogram of Oriented Gradient (HOG) features and Support Vector Machine (SVM) classification. Parallel detectors with balanced workload are used to enable processing of multiple scales and increase the throughput such that voltage scaling can be applied to reduce energy consumption. Image pre-processing is also introduced to further reduce power and area cost of the image scales generation. This design can operate on high definition 1080HD video at 60 fps in real-time with a clock rate of 270 MHz, and consumes 45.3 mW (0.36 nJ/pixel) based on post-layout simulations. The ASIC has an area of 490 kgates and 0.538 Mbit on-chip memory in a 45nm SOI CMOS process.

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FPGA-Based Real-Time Pedestrian Detection on High-Resolution Images

Cited by 97 publications

References 11 publications

FPGA Accelerated Pedestrian Detection System

FPGA Accelerated Pedestrian Detection System

Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs

Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support

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