FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control

Majzoobi, Mehrdad; Koushanfar, Farinaz; Devadas, Srinivas

doi:10.1007/978-3-642-23951-9_2

Cited by 99 publications

(67 citation statements)

References 12 publications

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“…In 2011, M. Majzoobi et al [7] used the Programmable Delay Lines (PDL) to control precisely trigger propagation delay of the flip-flop, which makes the Fig. 1.…”

Section: Metastable Statementioning

confidence: 99%

“…Due to the thermal noise of the circuit, the output fluctuates slightly in the meta-stable region. When the switch is turned off, the output of the inverter will quickly change from the meta-stable state into a steady state [7]. At that time it is uncertain that the output of the inverter become high or low for the semiconductor thermal noise.…”

Section: Metastable Statementioning

confidence: 99%

See 1 more Smart Citation

A true random number generator based on meta-stable state

Fan

Long

Luo

et al. 2018

IEICE Electron. Express

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This paper presents a ring oscillator structure which combines meta-stable states with Fibonacci ring oscillators (FIRO) and Galois ring oscillators (GAROs). Based on the new structure, a true random number generator (TRNG) of 64 bit was created. This new TRNG was verified by FPGA platform with Altera Cyclone IV series chips, and its output has attainted NIST SP800-22 certification. The testing demonstrates that the proposed meta-stable random number generators improve randomness over traditional methodologies.

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“…In 2011, M. Majzoobi et al [7] used the Programmable Delay Lines (PDL) to control precisely trigger propagation delay of the flip-flop, which makes the Fig. 1.…”

Section: Metastable Statementioning

confidence: 99%

Section: Metastable Statementioning

confidence: 99%

A true random number generator based on meta-stable state

Fan

Long

Luo

et al. 2018

IEICE Electron. Express

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show abstract

“…For the Slender PUF protocol, it is desirable to use a low overhead PUF implementation, such as the one introduced in [23]. If an ASIC or analog implementation of the PUF is required, the ultra-low power architecture in [21] is suitable for this protocol.…”

Section: Hardware Implementationmentioning

confidence: 99%

“…We use the architecture presented in [23] to implement a true random number generator. The TRNG architecture is shown in Figure 8.…”

Section: Hardware Implementationmentioning

confidence: 99%

Slender PUF Protocol: A Lightweight, Robust, and Secure Authentication by Substring Matching

Majzoobi

Rostami

Koushanfar

et al. 2012

2012 IEEE Symposium on Security and Privacy Workshops

Self Cite

182

138

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Abstract-We introduce Slender PUF protocol, an efficient and secure method to authenticate the responses generated from a Strong Physical Unclonable Function (PUF). The new method is lightweight, and suitable for energy constrained platforms such as ultra-low power embedded systems for use in identification and authentication applications. The proposed protocol does not follow the classic paradigm of exposing the full PUF responses (or a transformation of the full string of responses) on the communication channel. Instead, random subsets of the responses are revealed and sent for authentication. The response patterns are used for authenticating the prover device with a very high probability. We perform a thorough analysis of the method's resiliency to various attacks which guides adjustment of our protocol parameters for an efficient and secure implementation. We demonstrate that Slender PUF protocol, if carefully designed, will be resilient against all known machine learning attacks. In addition, it has the great advantage of an inbuilt PUF error tolerance. Thus, Slender PUF protocol is lightweight and does not require costly additional error correction, fuzzy extractors, and hash modules suggested in most previously known PUF-based robust authentication techniques. The low overhead and practicality of the protocol are confirmed by a set of hardware implementation and evaluations.

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“…However, the extensive use of stochastic computation is still limited, because of its long run-time and inaccuracy. Recent improvements have mainly focused on improving the accuracy and performance of the stochastic circuits by sharing consecutive bit streams, sharing the stochastic number generators, using true random generators, exploiting the correlation and using the spectral approach for stochastic circuit synthesis [11][12][13][14][15][16][17]. This paper also explores new methods to improve the accuracy and performance of stochastic circuits.…”

Section: Introductionmentioning

confidence: 99%

Implementation Of Reconfigurability Number Generators For Digital Bit Stream Signals

2018

IJRTER

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The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bit stream processing and excessive runtime requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bit stream processing, which are well suited to leverage FPGA's reconfigurability and abundant internal memory resources. the proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively.

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FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control

Cited by 99 publications

References 12 publications

A true random number generator based on meta-stable state

A true random number generator based on meta-stable state

Slender PUF Protocol: A Lightweight, Robust, and Secure Authentication by Substring Matching

Implementation Of Reconfigurability Number Generators For Digital Bit Stream Signals

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