FPGA Blokus Duo Solver using a massively parallel architecture

Yoza, Takashi; Moriwaki, Retsu; Torigai, Yuki; Kamikubo, Yuki; Kubota, Takayuki; Watanabe, Takahiro; Fujimori, Takahiro; Ito, Hiroyuki; Seo, Masato; Akagi, Kouta; Yamaji, Youhei; Watanabe, Minoru

doi:10.1109/fpt.2013.6718426

Cited by 7 publications

(3 citation statements)

References 9 publications

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“…Other games like Connect6, Blokus and Go have also been implemented by the FPGA developer's community. The works presented in [15][16][17] detail FPGA-based implementations and comparisons with software, reporting speedups of one or even two orders of magnitude. In the light of these results, it is clear that FPGAs outperform general purpose processors in these games.…”

Section: Related Workmentioning

confidence: 99%

Accelerating Board Games Through Hardware/Software Codesign

Olivito

Resano

Briz

2017

IEEE Trans. Comput. Intell. AI Games

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Board games applications usually offer a great user experience when running on desktop computers. Powerful high performance processors working without energy restrictions successfully deal with the exploration of large game trees, delivering strong play to satisfy demanding users. However, nowadays, more and more game players are running these games on smartphones and tablets, where the lower computational power and limited power budget yield a much weaker play. Recent Systems-on-a-Chip include programmable logic tightly coupled with general-purpose processors enabling the inclusion of custom accelerators for any application to improve both performance and energy efficiency. In this article, we analyze the benefits of partitioning the artificial intelligence of board games into software and hardware. We have chosen as case studies three popular and complex board games, Reversi, Blokus, and Connect-6. The designs analyzed include hardware accelerators for board processing which improve performance and energy efficiency by an order of magnitude leading to much stronger and battery-aware applications. The results demonstrate that the use of hardware/software co-design to develop board games allows sustaining or even improving the user experience across platforms while keeping power and energy low.

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Section: Related Workmentioning

confidence: 99%

Accelerating Board Games Through Hardware/Software Codesign

Olivito

Resano

Briz

2017

IEEE Trans. Comput. Intell. AI Games

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“…Thanks to the availability of one-to-one mapping and the spatial and temporal parallelism of the FPGAs, they are often used to implement real-time image processing applications [6][7][8][9][10]. One such application is the game code implementation on FPGAs such as Tetris [11], Connect6 [12][13], Blokus duo [14][15][16], Trax [17] and Pong [18][19]. In [11], Kuo et al design a tetris game code using the Spartan 3AN FPGA starter board of Xilinx.…”

Section: Introductionmentioning

confidence: 99%

VHDL İle Tam Gömülü Bi̇r Tetri̇s Oyunu Gerçekleşti̇rmesi̇

Polat¹

2020

Ömer Halisdemir Üniversitesi Mühendislik Bilimleri Dergisi

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In this paper, a Tetris game code which runs on an FPGA development and education board is synthesized. To this end, an original Tetris game code that works solely on the FPGA board is designed in VHDL hardware description language. The novelty of this design lies in the fact that the Tetris code does not use any SRAM modules for storage unlike other embedded Tetris implementations published to date. What is more, the code uses a tile-mapped scheme in which the code groups certain pixels as a tile. Thus, a 1-bit register is enough for the current value of all the pixels that fall in the tile which improves the speed of the code and simplifies the design procedure. The code is written using VHDL hardware description language. Though Altera DE0 development and education board is used for the implementation, thanks to the usage of only the standard VHDL functions, the code can run on any other FPGA boards.

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“…In the contest, each design implemented on an FPGA board exchanges the move within one second, and plays the game. This contest was also held in ICFPT2013 and many participants competed [3], [4], [5], [6], [7], [8]. Since there are many patterns on placement of the tile in Blokus Duo, candidates of a move is more than 1000.…”

Section: Introductionmentioning

confidence: 99%

Hardware/software co-design architecture for Blokus Duo solver

Sugimoto

Amano

2014

2014 International Conference on Field-Programmable Technology (FPT)

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This paper presents a software and hardware design of an FPGA-based Blokus Duo solver. We used Embedded system called ZYNQ-7000 All Programmable SoC to implement the solver. By combining hardware with software, efficient acceleration is performed. Our system searches a game tree by using the miniMax algorithm with alpha-beta pruning. The implemented solver works at 75MHz with Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 on the Digilent ZedBoard. It can search states after three moves in most cases.

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FPGA Blokus Duo Solver using a massively parallel architecture

Cited by 7 publications

References 9 publications

Accelerating Board Games Through Hardware/Software Codesign

Accelerating Board Games Through Hardware/Software Codesign

VHDL İle Tam Gömülü Bi̇r Tetri̇s Oyunu Gerçekleşti̇rmesi̇

Hardware/software co-design architecture for Blokus Duo solver

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