FPGA-controlled PCBA power-on self-test using processor's debug features

Du, Boyang; Sánchez, Ernesto; Reorda, M. Sonza; Acle, Julio Pérez; Tsertov, Anton

doi:10.1109/ddecs.2016.7482458

Cited by 3 publications

(3 citation statements)

References 12 publications

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“…We developed techniques leading to more efficient board-level test exploiting a mix of embedded instrumentation and functional test. More specifically, we developed new techniques for the generation of functional tests able to exploit embedded instruments (in particular those offered by the debug interfaces [DU16]), identified new instruments specifically focusing on dynamic fault identification at the PCB level by hard-and/or software with reconfigurable statistics, duration and shapes controlled via boundary scan (BS) / test access port (TAP) controller at PCB level; optimization of the test in terms of duration and resource requirements [GAU15]; and automation of test generation and development of integrated PCB test platforms.…”

Section: Instrument-assisted Testing For Nffmentioning

confidence: 99%

“…The approach mimics what has been done in the recent past for microcontrollers and SoCs (by adding embedded instruments to be used for design validation, silicon debug, and test) and was extended to PCBs, taking advantage of the existence of software accessible embedded instruments that can significantly improve the fault observability. We also investigated the usage of other instruments, corresponding for example to the debug infrastructure [DU16] and performance counters which are present in many microprocessors [PER16], to better support functional test. Finally, the BASTION partners successfully investigated new solutions to increase the effectiveness of functional test programs [PER16] and to automate the generation of functional programs for testing permanent faults in small-and medium-sized processors [RIE16].…”

Section: Instrument-assisted Testing For Nffmentioning

confidence: 99%

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BASTION: Board and SoC test instrumentation for ageing and no failure found

Jutman¹,

Lotz²,

Larsson

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail.

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Section: Instrument-assisted Testing For Nffmentioning

confidence: 99%

Section: Instrument-assisted Testing For Nffmentioning

confidence: 99%

BASTION: Board and SoC test instrumentation for ageing and no failure found

Jutman¹,

Lotz²,

Larsson

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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show abstract

“…On the other hand, they can provide internal access to the microprocessor without disturbing it. In particular, the use of program trace interfaces has been proposed and demonstrated for soft cores [5], [6], [7]. In a soft core, it is possible to use a low-level or custom trace interface that provides great flexibility and performance.…”

Section: Introductionmentioning

confidence: 99%

PTM-based hybrid error-detection architecture for ARM microprocessors

Pena-Fernandez

Lindoso

Entrena

et al. 2018

Microelectronics Reliability

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This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS microprocessors because it does not modify the microprocessor architecture and is able to detect errors thanks to the reuse of its trace subsystem. Validation has been performed by proton irradiation and fault injection campaigns on a Zynq AP SoC including a Cortex-A9 ARM microprocessor and an implementation of the proposed hardware monitor in programmable logic. Experimental results demonstrate that a high error detection rate can be achieved on a commercial microprocessor.

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