FPGA Design and Performance Evaluation of a Pulse-Based Echo Canceller for DVB-T/H

Abstract

In this paper, we address the main design issues and performance characteristics of an echo canceller for digital DVB-T/H on-channel repeaters (OCRs). The low-complexity channel cancellation technique here described is based on the introduction of a negative feedback loop capable to counterbalance the coupling effects between the OCR antennas (echoes). In the initial phase, locally generated pulse trains are transmitted to estimate the coupling channel between the transmitting and the receiving antennas. This first echo estimation is used to set-up the cancelling unit, whose purpose is to generate a properly filtered replica of the repeated DVB-T/H signal compensating the echoes. After the initial set-up of the system, efficient tracking of the echoes can be performed through traditional least mean square (LMS) techniques. After developing a proper theoretical model, we introduce and discuss some important performance figures such as mean rejection ratio (MRR) and echo suppression at nominal position (ESNP). Then, a detailed description of our implementation of the echo canceller on a field programmable gate array (FPGA) board is reported. Finally, the performance of our prototype are evaluated and the measurement results are compared with those derived by our analytical model.

Performance and Stability Analysis of Echo Cancellers Based on Training Sequences

“…7. Workbench configuration: conceptual scheme realized to test the echo canceller (from [15]). the upper bound is not extremely tight, but, for increasing values of γ e , simulation results tend to the analytical bound (47).…”

“…It is worth observing here that, if the filtering process within the OCR is realized through a multi-rate architecture, the receiving filter may coincide with the first cascade of filtering and decimation stages, while the transmitting filter may be constituted by the subsequent cascade of interpolation and filtering stages [19]. This solution implies the further advantage that the echo cancelling unit would work at significant lower sample rate, thus reducing the requirements in terms of processing capabilities [15], [19].…”

“…In such as case, particular attention in setting the training sequence power has to be paid in order to make the interference effects on the repeated signal negligible at the end user as investigated in [14]. As an alternative, adaptive algorithms (e.g., based on LMS principles) can be usefully employed to improve the tracking capabilities of the cancelling unit [15]. In case of detection of some instability phenomenon during the steady-state mode, the switch S can be readily opened, in order to permit another fast initialization of the cancelling unit.…”

“…In this section we validate the system model and the analytical framework through a measurement campaign carried on the echo canceller prototype described in [14] and [15]. For a detailed description of implementation aspects, measurement instrumentation and workbench set-up we refer to the abovementioned papers.…”

RF Transceiver Circuit FPGA Program Design and Development

“…As for the processing of low IF band, the easy-integrated band-pass filter is used as the postfrequency filter. The low IF structure maintains its high performance also because it is not sensitive to noise, LO signal leakage, DC deviation and other problems [18]. The structural diagram of low RF front-end is shown in Figure 4: …”