FPGA design of a real-time implementation of dynamic range compression for improving television picture

Charoensak, C.; Sattar, F.

doi:10.1109/icics.2007.4449797

Cited by 11 publications

(8 citation statements)

References 5 publications

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“…Obviously, the proposed design achieves faster speed and lower cost than [9] and [13]. The authors of [9] have demonstrated that their architecture is better than those previous designs [10]- [12]. Thus, we can conclude that our design outperforms those previous designs [9]- [13].…”

Section: Implementation and Experimental Resultsmentioning

confidence: 61%

“…For real-time applications, hardware implementation of bilateral filtering is necessary. Several bilateral hardware designs [9]- [12] have been presented and implemented on fieldprogrammable gate arrays (FPGAs). The authors of [9] arranged the input data into groups and proposed a kernelbased design to process the entire 5 × 5 filter window at one pixel clock cycle.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…Table 1 lists the detailed processing steps, input and output of each step, number of required multipliers and pixel latency of [9]. Although [9] achieves better hardware resource utilization than [10]- [12], we find that their kernel-based structure can be improved further. By using distance-oriented grouping and resource sharing, we proposed a lower cost hardware in this paper.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…To improve the speed of bilateral filtering, several previous works [9]- [13] in hardware architecture have been implemented and presented on field-programmable gate arrays (FPGAs). In [9], the authors attempted to decrease the resource demand by sorting data into several groups and proposed a less expensive hardware architecture than other designs [10]- [12]. In this paper, a low-cost and real-time very large scale integrated (VLSI) architecture of a bilateral filter that does not adversely affect the quality of the image is proposed.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Cost VLSI Architecture of the Bilateral Filter for Real-Time Image Denoising

Lien¹,

Tang

Chen

et al. 2020

IEEE Access

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In this paper, a low-cost hardware architecture of the bilateral filter for real-time image processing is proposed. Based on the techniques of distance-oriented grouping and hardware resource sharing, the usage of multipliers can decrease 48% as compared to the previous approach. Besides, an efficient quantization method is applied to reduce the size of required look up tables. The experimental results show that the proposed architecture is cost efficient while maintaining the same image quality, frame rate and working clock frequency. INDEX TERMS Bilateral filter, image processing, noise reduction, real-time processing.

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Section: Implementation and Experimental Resultsmentioning

confidence: 61%

Section: Proposed Methodsmentioning

confidence: 99%

Section: Proposed Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Low-Cost VLSI Architecture of the Bilateral Filter for Real-Time Image Denoising

Lien¹,

Tang

Chen

et al. 2020

IEEE Access

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“…It is necessary to realize the real-time application of bilateral filtering algorithms by hardware. The authors of [10] proposed a kernel-based design where they use position-oriented grouping. A total of 23 multipliers are needed to deal with a 5×5 filtering window in one pixel clock cycle.…”

Section: A Vlsi Architecture Of the Bilateral Filtermentioning

confidence: 99%

Hardware oriented bilateral filter algorithm and architecture survey

Gong

2023

ACE

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Images and videos are often interfered with and affected by various noises. To filter out noise, researchers have proposed many filtering algorithms. bilateral filtering is a nonlinear filtering technique that can retain detailed information such as image edges well while denoising. However, it is a difficult task to implement fast and high-precision bilateral filtering algorithms in hardware platforms. In this paper, for the optimization of bilateral filtering algorithms, we analyze the gradient bilateral filtering and the piecewise approximate bilateral filtering algorithm that can be implemented in hardware, respectively. Then, we analyze and compare the implementation and optimization of bilateral filtering algorithms on FPGA and VLSI hardware architectures, and finally, make suggestions for choosing the appropriate bilateral filtering algorithms and hardware architectures for different purposes.

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An FPGA-based design for a real-time image denoising using approximated fractional integrator

Kumar

Jha

2020

Multidim Syst Sign Process

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FPGA design of a real-time implementation of dynamic range compression for improving television picture

Cited by 11 publications

References 5 publications

A Low-Cost VLSI Architecture of the Bilateral Filter for Real-Time Image Denoising

A Low-Cost VLSI Architecture of the Bilateral Filter for Real-Time Image Denoising

Hardware oriented bilateral filter algorithm and architecture survey

An FPGA-based design for a real-time image denoising using approximated fractional integrator

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