FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement

Malathi, L.; Bharathi, A.; Jayanthi, A.N.

doi:10.1016/j.bspc.2023.105599

Biomedical Signal Processing and Control

2024

DOI: 10.1016/j.bspc.2023.105599

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FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement

L. Malathi,

A. Bharathi,

A.N. Jayanthi

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2024

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Cited by 2 publications

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DSLR-CNN: Efficient CNN Acceleration Using Digit-Serial Left-to-Right Arithmetic

Nisar,

Ibrahim,

Gorgin

et al. 2024

IEEE Access

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DSLR-CNN: Efficient CNN Acceleration Using Digit-Serial Left-to-Right Arithmetic

Nisar,

Ibrahim,

Gorgin

et al. 2024

IEEE Access

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High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

BAYSAL,

TAŞKIN

2023

Sakarya University Journal of Computer and Information Sciences

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Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs. The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms. In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.

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FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement

Cited by 2 publications

References 19 publications

DSLR-CNN: Efficient CNN Acceleration Using Digit-Serial Left-to-Right Arithmetic

DSLR-CNN: Efficient CNN Acceleration Using Digit-Serial Left-to-Right Arithmetic

High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

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