FPGA Implementation and Design of a Hybrid Chaos-AES Color Image Encryption Algorithm

Yang, Cheng-Hsiung; Chien, Yu-Sheng

doi:10.3390/sym12020189

Cited by 31 publications

(13 citation statements)

References 26 publications

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“…Block encryption algorithms are ineffective in the encryption of digital images. One of the most important reasons for this problem is the high correlation between the pixel values of an image [38]. Usually, images are represented by a matrix with a size of m × n .…”

Section: Detail Of Proposed Methodsmentioning

confidence: 99%

A Novel Method for Performance Improvement of Chaos-Based Substitution Boxes

Artuğer

Özkaynak

2020

Symmetry

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Symmetry plays an important role in nonlinear system theory. In particular, it offers several methods by which to understand and model the chaotic behavior of mathematical, physical and biological systems. This study examines chaotic behavior in the field of information security. A novel method is proposed to improve the performance of chaos-based substitution box structures. Substitution box structures have a special role in block cipher algorithms, since they are the only nonlinear components in substitution permutation network architectures. However, the substitution box structures used in modern block encryption algorithms contain various vulnerabilities to side-channel attacks. Recent studies have shown that chaos-based designs can offer a variety of opportunities to prevent side-channel attacks. However, the problem of chaos-based designs is that substitution box performance criteria are worse than designs based on mathematical transformation. In this study, a postprocessing algorithm is proposed to improve the performance of chaos-based designs. The analysis results show that the proposed method can improve the performance criteria. The importance of these results is that chaos-based designs may offer opportunities for other practical applications in addition to the prevention of side-channel attacks.

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Section: Detail Of Proposed Methodsmentioning

confidence: 99%

A Novel Method for Performance Improvement of Chaos-Based Substitution Boxes

Artuğer

Özkaynak

2020

Symmetry

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“…Yang, Cheng, et al [58] proposed a four-dimensional chaotic method to produce keys and boost the Advanced Encryption Standard. Using FPGA pipelines and parallel processing, the encryption algorithm is simplified as the secret to the encryption algorithm is the chaotic process.…”

Section: Literature Reviewmentioning

confidence: 99%

FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review

Yazdeen

Zeebaree

Sadeeq

et al. 2021

QAJ

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In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic encryption, symmetrical block chips play an essential role. Data Encryption Standard (DES) and Advanced Encryption Standard (AES) ensure privacy encryption underlying data protection standards. The DES and the AES provide information security. DES and AES have the distinction of being introduced in both hardware and applications. DES and AES hardware implementation has many advantages, such as increased performance and improved safety. This paper provides an exhaustive study of the implementation by DES and AES of field programming gate arrays (FPGAs) using both DES and AES. Since FPGAs can be defined as just one mission, computers are superior to them.

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“…A combined-block strategy employing Key Expansion design for improving the throughput and for minimizing the power usage was introduced by Kalaiselvi [22]. In numerous additional scientific studies [23][24][25][26][27], various degrees of pipelined architectures were suggested. Granado et al [28] created a high-speed AES formula execution for Wi-FI Protected Access 2 (WPA2) systems.…”

Section: Literature Reviewmentioning

confidence: 99%

Advanced FPGA Implementation of AES Algorithm

2021

IJETER

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Along with the enhance in computation as well as information safe-keeping in cloud servers, the requirement for a devoted computer hardware accelerator with regard to encryption is arising to be able to decrease the processor work. Highly efficient Advanced Encryption Standard (AES) 128-bit implementation, that could be utilized as an accelerator. In this research paper resource optimization and higher throughput were obtained. Memory segmentation is actually carried out to be able to assign several ports for simultaneous information accessibility. When algorithm is in proceed and examined time delay and initiation time period of various procedures, with regard to every crucial route delay, a fresh multistage solitary initiation time period sub-pipelined structure is suggested for making the initiation time period to a single for smallest route latency. Consequently, almost all operations in AES could be started within a single clock cycle and also can easily accept input in each and every clock cycle. The suggested approach while examined on latest Field Programmable Gate Array (FPGA) XC7VX690T unit that offers a throughput of 104.06 Gbps at a highest frequency of 813MHz and also 1.23-ns route delay. The useful resource utilization is reduced whenever compared along with other alternatives. The suggested method offers 30.74Mbps efficiency on device, which usually was 27.13% much more compared to the best efficiency documented in an earlier research study

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FPGA Implementation and Design of a Hybrid Chaos-AES Color Image Encryption Algorithm

Cited by 31 publications

References 26 publications

A Novel Method for Performance Improvement of Chaos-Based Substitution Boxes

A Novel Method for Performance Improvement of Chaos-Based Substitution Boxes

FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review

Advanced FPGA Implementation of AES Algorithm

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